Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.

Abstract: Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.

Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.

Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.

Abstract: Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support a substrate, a shaft coupled to the stage, a first heating element disposed within a central region of the body of the stage, and at least second and third heating elements disposed within the body of the stage, the at least second and third heating elements each partially surrounding the first heating element and wherein the at least second and third heating elements are circumferentially adjacent to each other.

Abstract: A back contact solar cell is described which includes a semiconductor light absorbing layer; a first-level metal layer (M1), the M1 metal layer on a back side of the light absorbing layer, the back side being opposite from a front side of the light absorbing layer designed to receive incident light; an electrically insulating backplane sheet backside of said solar cell with the M1 layer, the backplane sheet comprising a plurality of via holes that expose portions of the M1 layer beneath the backplane sheet; and an M2 layer in contact with the backplane sheet, the M2 layer made of a sheet of pre-fabricated metal foil material comprising a thickness of between 5-250 ?m, the M2 layer electrically connected to the M1 layer through the via holes in the backplane sheet.

Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions and passivation layers using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions. Laser damage to the solar cell substrate is removed using an etch.

Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions and passivation layers using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions.

Abstract: Laser patterning methods utilize a laser absorbent hard mask in combination with wet etching to form patterned solar cell doped regions to improve cell efficiency by avoiding laser ablation of an underlying semiconductor substrate associated with ablation of an overlying transparent passivation layer.

Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided.

Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions.