Patents by Inventor Sean M. Seutter

Sean M. Seutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9012334
    Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Publication number: 20150101662
    Abstract: Stable surface passivation on a crystalline silicon substrate is provided by forming a more heavily doped region as a front surface field and/or a doped dielectric layer under a passivation layer on the silicon substrate surface. A passivation layer is deposited on the front surface field and/or doped dielectric layer.
    Type: Application
    Filed: July 7, 2014
    Publication date: April 16, 2015
    Inventors: Sean M. Seutter, Mehrdad M. Moslehi
  • Patent number: 8946547
    Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 3, 2015
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Karl-Josef Kramer, Sean M. Seutter, Sam Tone Tor, Anthony Calcaterra
  • Publication number: 20140158193
    Abstract: Fabrication methods and structures relating to back contact solar cells having patterned emitter and non-nested base regions are provided.
    Type: Application
    Filed: May 29, 2013
    Publication date: June 12, 2014
    Inventors: Anande Desphande, Pawan Kapur, Heather Deshazer, Mehrdad M. Moslehi, Virendra V. Rana, Sean M. Seutter, Pranav Anbalagan, Benjamin E. Rattle, Solene Coutant, Swaroop Kommera
  • Publication number: 20130167915
    Abstract: Back contact back junction three dimensional solar cell and methods for manufacturing are provided. The back contact back contact back junction three dimensional solar cell comprises a three-dimensional substrate. The substrate comprises a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer is positioned on the doped backside emitter region. Backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of three-dimensional solar cell.
    Type: Application
    Filed: December 9, 2010
    Publication date: July 4, 2013
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, David Xuan-Qi Wang, Sean M. Seutter, Virenda V. Rana
  • Publication number: 20130164883
    Abstract: Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional.
    Type: Application
    Filed: November 23, 2011
    Publication date: June 27, 2013
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Virendra V. Rana, Sean M. Seutter, Anand Deshpande
  • Publication number: 20130000715
    Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, attaching a prepeg backplane to the interdigitated pattern of base electrodes and emitter electrodes, forming holes in the prepeg backplane which provide access to the first layer of electrically conductive metal, and depositing a second layer of electrically conductive metal on the backside surface of the prepeg backplane forming an electrical interconnect with the first layer of electrically conductive metal through the holes in the prepeg backplane.
    Type: Application
    Filed: March 28, 2012
    Publication date: January 3, 2013
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Karl-Josef Kramer, Sean M. Seutter, Sam Tone Tor, Anthony Calcaterra
  • Publication number: 20120305063
    Abstract: Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell.
    Type: Application
    Filed: December 9, 2010
    Publication date: December 6, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, David Xuan-Qi Wang, Sean M. Seutter, Virenda V. Rana, Anthony Calcaterra, Emmanuel Van Kerschaver
  • Publication number: 20120178256
    Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
    Type: Application
    Filed: February 14, 2012
    Publication date: July 12, 2012
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Publication number: 20120103408
    Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.
    Type: Application
    Filed: August 5, 2011
    Publication date: May 3, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Karl-Josef Kramer, Sean M. Seutter, Sam Tone Tor, Anthony Calcaterra
  • Patent number: 8114789
    Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 14, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Publication number: 20110284068
    Abstract: The disclosed subject matter provides a method and structure for obtaining ultra-low surface recombination velocities from highly efficient surface passivation in crystalline silicon substrate-based solar cells by utilizing a bi-layer passivation scheme which also works as an efficient ARC. The bi-layer passivation consists of a first thin layer of wet chemical oxide or a thin hydrogenated amorphous silicon layer. A second layer of amorphous hydrogenated silicon nitride film is deposited on top of the wet chemical oxide or amorphous silicon film. This deposition is then followed by annealing to further enhance the surface passivation.
    Type: Application
    Filed: April 23, 2011
    Publication date: November 24, 2011
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, Anand Deshpande, Rafael Ricolcol, Sean M. Seutter
  • Publication number: 20110281429
    Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 17, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Christopher S. Olsen, Sean M. Seutter, Lucien Date
  • Publication number: 20110101442
    Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Christopher S. Olsen, Sean M. Seutter, Lucien Date
  • Patent number: 7922863
    Abstract: An apparatus for photo-assisted or photo-induced processes is disclosed, comprising a process chamber having an integrated gas and radiation distribution plate. In one embodiment, the plate has one set of apertures for distributing one or more process gases, and another set of apertures for distributing radiation to a process region in the chamber.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Martin John Ripley, Sean M. Seutter
  • Publication number: 20100311237
    Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
    Type: Application
    Filed: July 29, 2010
    Publication date: December 9, 2010
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Publication number: 20100294199
    Abstract: Embodiments of the invention provide improved apparatus for depositing layers on substrates, such as by chemical vapor deposition (CVD). The inventive apparatus disclosed herein may advantageously facilitate one or more of depositing films having reduced film thickness non-uniformity within a given process chamber, improved particle performance (e.g., reduced particles on films formed in the process chamber), chamber-to-chamber performance matching amongst a plurality of process chambers, and improved process chamber serviceability.
    Type: Application
    Filed: April 20, 2010
    Publication date: November 25, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: BINH TRAN, ANQING CUI, BERNARD L. HWANG, SON T. NGUYEN, ANH N. NGUYEN, SEAN M. SEUTTER, XIANZHI TAO
  • Patent number: 7781326
    Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: August 24, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Michael X. Yang, Ming Xi
  • Publication number: 20090314762
    Abstract: Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support a substrate, a shaft coupled to the stage, a first heating element disposed within a central region of the body of the stage, and at least second and third heating elements disposed within the body of the stage, the at least second and third heating elements each partially surrounding the first heating element and wherein the at least second and third heating elements are circumferentially adjacent to each other.
    Type: Application
    Filed: June 16, 2009
    Publication date: December 24, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Anqing Cui, Binh Tran, Alexander Tam, Jacob W. Smith, R. Suryanarayanan Iyer, Joseph Yudovsky, Sean M. Seutter
  • Patent number: 7601652
    Abstract: Embodiments of the invention generally provide a method for depositing films using photoexcitation. The photoexcitation may be utilized for at least one of treating the substrate prior to deposition, treating substrate and/or gases during deposition, treating a deposited film, or for enhancing chamber cleaning. In one embodiment, a method for depositing silicon and nitrogen-containing film on a substrate includes heating a substrate disposed in a processing chamber, generating a beam of energy of between about 1 to about 10 eV, transferring the energy to a surface of the substrate; flowing a nitrogen-containing chemical into the processing chamber, flowing a silicon-containing chemical with silicon-nitrogen bonds into the processing chamber, and depositing a silicon and nitrogen-containing film on the substrate.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Sean M. Seutter, Jacob Smith, R. Suryanarayanan Iyer, Steve G. Ghanayem, Adam Brailove, Robert Shydo, Jeannot Morin