Patents by Inventor Seiji Funaba
Seiji Funaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110031939Abstract: A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor.Type: ApplicationFiled: August 6, 2010Publication date: February 10, 2011Applicant: Hitachi Automotive Systems, Ltd.Inventors: Seiji Funaba, Yasuo Noto, Masashige Tsuji
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Patent number: 7856072Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: GrantFiled: June 10, 2009Date of Patent: December 21, 2010Assignee: Elpida Memory, Inc.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Patent number: 7768867Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: GrantFiled: June 12, 2007Date of Patent: August 3, 2010Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Yutaka Uematsu, Seiji Funaba, Hideki Osaka, Tsutomu Hara, Koichiro Aoki
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Patent number: 7760531Abstract: A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.Type: GrantFiled: August 29, 2006Date of Patent: July 20, 2010Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Seiji Funaba, Yutaka Uematsu, Hideki Osaka
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Patent number: 7725778Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.Type: GrantFiled: December 8, 2008Date of Patent: May 25, 2010Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7689944Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.Type: GrantFiled: August 29, 2006Date of Patent: March 30, 2010Assignee: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Satoshi Isa, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose
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Patent number: 7656744Abstract: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.Type: GrantFiled: December 14, 2006Date of Patent: February 2, 2010Assignee: Elpida Memory, Inc.Inventors: Yurika Aoki, Seiji Funaba, Yoji Nishio
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Patent number: 7633147Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.Type: GrantFiled: September 26, 2003Date of Patent: December 15, 2009Assignees: Elpida Memory, Inc., Renesas Eastern Japan Semiconductor, Inc.Inventors: Seiji Funaba, Hisashi Abo, Takao Ono, Koji Hosokawa, Yoji Nishio, Atsushi Nakamura, Tomohiko Sato
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Publication number: 20090245424Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: ApplicationFiled: June 10, 2009Publication date: October 1, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Patent number: 7558336Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: GrantFiled: November 8, 2004Date of Patent: July 7, 2009Assignee: Elpida Memory, Inc.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Publication number: 20090115442Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.Type: ApplicationFiled: December 8, 2008Publication date: May 7, 2009Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7478287Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.Type: GrantFiled: November 10, 2005Date of Patent: January 13, 2009Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7447038Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.Type: GrantFiled: December 16, 2005Date of Patent: November 4, 2008Assignee: Elpida Memory, Inc.Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Seiji Funaba
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Publication number: 20080203554Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.Type: ApplicationFiled: May 1, 2008Publication date: August 28, 2008Applicant: ELPIDA MEMORY INC.Inventors: Yoji NISHIO, Seiji FUNABA
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Patent number: 7411806Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: GrantFiled: December 6, 2006Date of Patent: August 12, 2008Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata
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Patent number: 7385281Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.Type: GrantFiled: December 23, 2004Date of Patent: June 10, 2008Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Seiji Funaba
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Publication number: 20080054379Abstract: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.Type: ApplicationFiled: February 15, 2007Publication date: March 6, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yoji Nishio, Yutaka Uematsu, Hideki Osaka, Tsutomu Hara, Seiji Funaba
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Publication number: 20080040081Abstract: In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.Type: ApplicationFiled: February 16, 2007Publication date: February 14, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yoji NISHIO, Seiji Funaba, Yurika Aoki, Kazuyoshi Shoji, Koji Matsuo, Mariko Otsuka, Ryuichi Ikematsu, Sadahiro Nonoyama, Kae Fujii
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Publication number: 20070291557Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: ApplicationFiled: June 12, 2007Publication date: December 20, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Yoji NISHIO, Yutaka UEMATSU, Seiji FUNABA, Hideki OSAKA, Tsutomu HARA, Koichiro AOKI
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Patent number: RE40205Abstract: Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit.Type: GrantFiled: August 23, 2002Date of Patent: April 1, 2008Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio, Yuichi Okuda, Yoshinobu Nakagome