Patents by Inventor Seiji Funaba
Seiji Funaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070255983Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.Type: ApplicationFiled: November 10, 2005Publication date: November 1, 2007Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7282791Abstract: A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.Type: GrantFiled: July 8, 2005Date of Patent: October 16, 2007Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7239169Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.Type: GrantFiled: August 23, 2002Date of Patent: July 3, 2007Assignee: Elpida Memory, Inc.Inventors: Satoshi Isa, Seiji Funaba
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Publication number: 20070140040Abstract: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.Type: ApplicationFiled: December 14, 2006Publication date: June 21, 2007Applicant: ELPIDA MEMORY, INCInventors: Yurika Aoki, Seiji Funaba, Yoji Nishio
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Publication number: 20070085601Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.Type: ApplicationFiled: October 13, 2006Publication date: April 19, 2007Inventors: Yoji Idei, Susumu Hatano, Yoji Nishio, Seiji Funaba, Yutaka Uematsu
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Publication number: 20070081376Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: ApplicationFiled: December 6, 2006Publication date: April 12, 2007Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata
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Publication number: 20070057380Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.Type: ApplicationFiled: August 29, 2006Publication date: March 15, 2007Inventors: Mitsuaki Katagiri, Satoshi Nakamura, Takashi Suga, Satoshi Isa, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose
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Publication number: 20070047354Abstract: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.Type: ApplicationFiled: August 29, 2006Publication date: March 1, 2007Inventors: Yoji Nishio, Seiji Funaba, Yutaka Uematsu, Hideki Osaka
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Patent number: 7161820Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.Type: GrantFiled: July 28, 2003Date of Patent: January 9, 2007Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio, Kayoko Shibata
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Patent number: 7102905Abstract: A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.Type: GrantFiled: November 3, 2004Date of Patent: September 5, 2006Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio
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Patent number: 7095661Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.Type: GrantFiled: December 23, 2004Date of Patent: August 22, 2006Assignee: Elpida Memory, Inc.Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba
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Publication number: 20060133055Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.Type: ApplicationFiled: December 16, 2005Publication date: June 22, 2006Inventors: Yutaka Uematsu, Hideki Osaka, Yoji Nishio, Seiji Funaba
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Patent number: 7051225Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.Type: GrantFiled: April 30, 2003Date of Patent: May 23, 2006Assignee: Elpida Memory Inc.Inventors: Yoji Nishio, Kayoko Shibata, Seiji Funaba
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Patent number: 7038498Abstract: Disclosed is an input/output circuit having a terminating circuit that contributes to a smaller chip area. The input/output includes an output buffer having a first series circuit, which comprises a first transistor and a resistor and a second series circuit, which comprises a second transistor and a resistor, connected in parallel between a high-potential power supply and an input/output pin, as well as a third series circuit, which comprises a third transistor and a resistor and a fourth series circuit, which comprises a fourth transistor and a resistor, connected in parallel between the input/output pin and a low-potential power supply.Type: GrantFiled: December 1, 2004Date of Patent: May 2, 2006Assignee: Elpida Memory, Inc.Inventor: Seiji Funaba
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Patent number: 7016212Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N?1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N?1)×Zeffdimm/N2.Type: GrantFiled: July 29, 2003Date of Patent: March 21, 2006Assignee: Elpida Memory Inc.Inventors: Kayoko Shibata, Yoji Nishio, Seiji Funaba
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Publication number: 20060018407Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.Type: ApplicationFiled: November 8, 2004Publication date: January 26, 2006Inventors: Hideki Osaka, Yoji Nishio, Seiji Funaba, Kazuyoshi Shoji
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Publication number: 20060006516Abstract: A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.Type: ApplicationFiled: July 8, 2005Publication date: January 12, 2006Inventors: Seiji Funaba, Yoji Nishio
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Register capable of corresponding to wide frequency band and signal generating method using the same
Patent number: 6986072Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.Type: GrantFiled: July 29, 2002Date of Patent: January 10, 2006Assignees: Elpida Memory, Inc., Hitachi Tohbu Semiconductor, Ltd., Hitachi, Ltd.Inventors: Yoji Nishio, Seiji Funaba, Kayoko Shibata, Toshio Sugano, Hiroaki Ikeda, Takuo Iizuka, Masayuki Sorimachi -
Patent number: 6985009Abstract: Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line.Type: GrantFiled: April 2, 2004Date of Patent: January 10, 2006Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Seiji Funaba
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Patent number: 6970369Abstract: In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.Type: GrantFiled: September 4, 2002Date of Patent: November 29, 2005Assignee: Elpida Memory, Inc.Inventors: Seiji Funaba, Yoji Nishio