Patents by Inventor Seiji Maeda

Seiji Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170255562
    Abstract: According to an embodiment, a cache device has a data memory capable of storing a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form, and a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including a piece of uncompressed data writing state information, an absence flag, and a compression information field.
    Type: Application
    Filed: September 19, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki USUI, Seiji MAEDA
  • Patent number: 9684602
    Abstract: A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiji Maeda
  • Patent number: 9619386
    Abstract: According to an embodiment, a synchronization variable monitoring device includes: an address comparator configured to compare a received address included in an Invalidate Request, and an address that is set as an address of synchronization variable data upon receiving the Invalidate Request; a readout circuit configured to read out data of the address of the synchronization variable data when the received address and the address of the synchronization variable data coincide with each other; a conditional variable comparator configured to determine whether or not a predetermined condition is satisfied based on the data read out by the readout circuit; and a synchronization completion flag register configured to output a synchronization signal indicating that a synchronization condition is satisfied when the conditional variable comparator determines that the predetermined condition is satisfied.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiji Maeda
  • Patent number: 9600234
    Abstract: A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiji Maeda
  • Publication number: 20170017573
    Abstract: A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to record, in response to a writing request for data from an input apparatus, management information of a first address region in which the data is stored, a reading request management unit configured to record a second address specified in a reading request from a storage apparatus and a control unit configured to receive the writing request and the reading request, and control processing of the reading request and updating of the update region management unit and the reading request management unit.
    Type: Application
    Filed: November 16, 2015
    Publication date: January 19, 2017
    Inventor: Seiji Maeda
  • Patent number: 9487650
    Abstract: Disclosed is a resin composition comprising a melt-moldable side chain 1,2-diol-containing PVA-based resin (A), and fluororesin containing a polar functional group capable of reacting with or forming hydrogen bond(s) with hydroxyl group (B). The component (A) and the component (B) have excellent affinity, and therefore if either the component (A) or component (B) becomes matrix, the other can be finely dispersed into the matrix, thus providing a resin composition having excellent gas-barrier property, solvent resistance, and bending fatigue resistance. The present invention also provides emulsified dispersion and binder in which the resin composition is used.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: November 8, 2016
    Assignees: THE NIPPON SYNTHETIC CHEMICAL INDUSTRY CO., LTD., ASAHI GLASS COMPANY, LIMITED
    Inventors: Mitsuo Shibutani, Akinobu Inakuma, Yasuhiro Hirano, Seiji Maeda, Eiichi Nishi, Shigeru Aida, Shintaro Fukunaga
  • Patent number: 9483442
    Abstract: According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Maeda, Hiroyuki Usui
  • Publication number: 20160267010
    Abstract: A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.
    Type: Application
    Filed: November 3, 2015
    Publication date: September 15, 2016
    Inventor: Seiji MAEDA
  • Publication number: 20160224470
    Abstract: According to an embodiment, a synchronization variable monitoring device includes: an address comparator configured to compare a received address included in an Invalidate Request, and an address that is set as an address of synchronization variable data upon receiving the Invalidate Request; a readout circuit configured to read out data of the address of the synchronization variable data when the received address and the address of the synchronization variable data coincide with each other; a conditional variable comparator configured to determine whether or not a predetermined condition is satisfied based on the data read out by the readout circuit; and a synchronization completion flag register configured to output a synchronization signal indicating that a synchronization condition is satisfied when the conditional variable comparator determines that the predetermined condition is satisfied.
    Type: Application
    Filed: June 1, 2015
    Publication date: August 4, 2016
    Inventor: Seiji MAEDA
  • Publication number: 20160070536
    Abstract: A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result.
    Type: Application
    Filed: March 10, 2015
    Publication date: March 10, 2016
    Inventor: Seiji Maeda
  • Publication number: 20160070649
    Abstract: According to an embodiment, a cache unit includes: a first memory configured to temporarily hold data and an address of the data, a second memory configured to temporarily hold an address of particular data set in advance, and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.
    Type: Application
    Filed: March 9, 2015
    Publication date: March 10, 2016
    Inventor: Seiji MAEDA
  • Patent number: 9267912
    Abstract: A gas information estimation apparatus (100) is connected to a gas sensor element for detecting the concentration of gas flowing through an internal combustion engine (11), and estimates gas information other than the concentration. The apparatus includes gas sensor element provisional temperature calculation means (51) for calculating a provisional temperature of the gas sensor element using a predetermined simulation model, and inputting a reference value to the model as the parameter value; gas sensor element actual temperature measurement means (53), (54); gas information calculation means (55) for calculating the true value of the parameter value which can be input to the model in place of the reference value such that the provisional temperature of the gas sensor element approaches the actual temperature; and gas information obtaining means (57) for obtaining an estimative value of the gas information from the true value.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 23, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Seiji Maeda
  • Publication number: 20150261675
    Abstract: An information processing device of an embodiment has an input unit, a storage unit, a read control unit, and a write control unit. A read request and a write request are input to the input unit. The storage unit stores management information. When the read request is input, the read control unit reads read data including the management information from the storage unit, references the management information, and outputs only non-zero data included in a predetermined range of a block row. The write control unit writes only non-zero data to the storage unit and updates the management information immediately before a start position of the continuous non-zero data started from a largest position in the continuous non-zero data started from a position smaller than the predetermined range, a last management information stored in the predetermined range, and the last management information in the predetermined range.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Inventors: Hiroyuki USUI, Seiji MAEDA
  • Patent number: 9081711
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 14, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Publication number: 20150081752
    Abstract: According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Maeda, Hiroyuki Usui
  • Patent number: 8961761
    Abstract: An oxygen sensor control apparatus includes internal resistance detection means S3, controlled internal resistance obtaining means S4 to S11, and heater energization control means S12. When a timing for detecting the internal resistance R(n) comes during a lean period TL, the controlled internal resistance obtaining means uses the detected internal resistance R(n) as the controlled internal resistance Rf. When a timing for detecting the internal resistance R(n) comes during a rich period TR, the controlled internal resistance obtaining means uses, as the controlled internal resistance Rf, a value obtained by correcting the detected internal resistance R(n) on the basis of a latest lean resistance R(k) such that a variation of the internal resistance which stems from the difference between the lean state and the rich state and which is contained in the detected internal resistance R(n) is removed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 24, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Seiji Maeda
  • Publication number: 20150038633
    Abstract: Disclosed is a resin composition comprising a melt-moldable side chain 1,2-diol-containing PVA-based resin (A), and fluororesin containing a polar functional group capable of reacting with or forming hydrogen bond(s) with hydroxyl group (B). The component (A) and the component (B) have excellent affinity, and therefore if either the component (A) or component (B) becomes matrix, the other can be finely dispersed into the matrix, thus providing a resin composition having excellent gas-barrier property, solvent resistance, and bending fatigue resistance. The present invention also provides emulsified dispersion and binder in which the resin composition is used.
    Type: Application
    Filed: April 26, 2013
    Publication date: February 5, 2015
    Inventors: Mitsuo Shibutani, Akinobu Inakuma, Yasuhiro Hirano, Seiji Maeda, Eiichi Nishi, Shigeru Aida, Shintaro Fukunaga
  • Patent number: 8949572
    Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
  • Patent number: D719924
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 23, 2014
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Satoshi Ueno, Seiji Maeda, Akira Tanikawa
  • Patent number: D741819
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: October 27, 2015
    Assignee: HOKURIKU ELECTRIC INDUSTRY CO., LTD.
    Inventors: Satoshi Ueno, Seiji Maeda, Akira Tanikawa