Abstract: A processor includes a setting register in which a mode is set, a general-purpose register including a preferred slot used during scalar computing and a slot not used during the scalar computing, a selector configured to select and output data of a register designated by a mode set in the setting register during the scalar computing, and a computing unit configured to execute the scalar computing using the preferred slot of the general-purpose register and store computing result data of the scalar computing in the preferred slot of the general-purpose register. The data of the register output from the selector is stored in the slot of the general-purpose register.

Abstract: The present invention provides a sheet for sealing a rear surface of a solar cell in which degradation due to hydrolysis of the material constituting the solar cell is prevented, and the weather resistance is excellent such that electric output properties of the solar cell can be maintained not only under conditions of actual usage of the solar cell module but also conditions for evaluation under high temperatures and high moistures, and provides a sheet for sealing a rear surface of a solar cell comprising a laminate in which at least two substrates are laminated by an polyurethane-based adhesive, wherein the polyurethane-based adhesive comprises an adhesive having hydrolysis resistance which satisfies the following conditions: condition 1: the lamination strength of the adhesive is 1 N/15 mm or more after keeping the laminate in a chamber which acts as a highly accelerated stress test system under pressurized steam conditions of 105° C. and 1.

Abstract: Schedulability determination method of determining whether real-time scheduling of tasks is possible using processors, includes calculating Lk and ?i=1 . . . NMi*Uk, i, (1?k, i?N; k, i: integer) where Lk corresponds to task-k, Mi represents number of the one or more processors simultaneously used by task-i, Uk, i corresponds to task-k and task-i, and N represents number of tasks, and determining that real-time scheduling of tasks is possible using processors, if tasks all satisfy conditions, ?i=1 . . .

Abstract: Process migration method includes copying first process context indicative of first processing, transmitting process context to second computer, causing first computer to start generation of first execution record, causing second computer to receive process context, determining, from first execution record, whether first processing should be migrated, if it is determined that first processing should postpone being migrated, finishing generation of first execution record, starting generation of second execution record, transmitting first execution record to second computer, reproducing process context, and determining, from second execution record, whether first processing should be migrated, after reproducing of process context is finished in the second computer.

Abstract: A harvesting device for an endoscope includes a harvesting member inserted through an outer tube member, including a harvesting portion arranged at the distal end portion of the outer tube member and to perform a harvesting, and configured to move so that the harvesting member moves and positions the harvesting portion at a harvesting position and a standby position, a wipe member inserted through the outer tube member, including a wipe portion arranged at the distal end portion of the outer tube member, and configured to move so that the wipe member moves the wipe portion to wipe a distal end portion of the endoscope, and a conversion mechanism to convert the movement of the harvesting member into that of the wipe member to interlock the wiping of the wipe portion with the positioning of the harvesting portion.

Abstract: According to an aspect of the present invention, the processor temperatures can be leveled among processors, thereby suppressing the occurrence of stop of processing due to overheating. For example, on the basis of the temperatures of the processors sensed by temperature sensors, the control IC assigns the processor whose temperature is the lowest to the task whose heat emission is the highest. This makes it possible to level the processor temperatures among processors and suppress occurrence of stop of processing due to overheating.

Abstract: An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.

Abstract: An information processing system includes a first processor that accesses a first memory, a second processor that accesses a second memory, and a data transfer unit for executing data transfer between the first memory and the second memory. The first processor executes functions of translating an instruction out of instructions included in the program except a memory access instruction into an instruction for the second processor and translating the memory access instruction into an instruction sequence containing a call instruction of the program to transfer the access data on the first memory to the second memory via a data transfer unit.

Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.

Abstract: A waterproof push button switch does not need to be covered with a resin to a height at which a divided connected portion of a case for the switch is hidden by the resin in a height direction and the divided connected portion may be waterproofed. A gap (55, 57) is formed between a peripheral wall portion 7b of a base case 7 and a second cylindrical wall portion 9b of a cover case 9, and between an opposite surface 41 of the cover case 9 and a waterproofing seal member 11. The gap (55, 57) extends from an opening portion of the base case fitting chamber 37 to an annular watertight seal portion 51 to completely surround a periphery of the watertight seal portion 51. The thickness of the gap portion 55 is determined so that the resin entered into the gap portion 55 from an opening portion 37a of the base case fitting chamber 37 reaches the watertight seal portion 51 by surface tension.

Abstract: An information processing system performs a plurality of tasks within a specific time interval. The system includes a bus, a plurality of processors which transfer data via the bus, and a unit for performing a scheduling operation of determining execution start timing of each of the tasks and at least one the processors which executes the tasks, based on cost information concerning a time required to perform each of the tasks and bandwidth information concerning a data transfer bandwidth required by each of the tasks, to perform the tasks within the specific time interval without overlapping execution terms of at least two tasks of the tasks, the two tasks requiring data transfer bandwidths not less than those of the others of the tasks.

Abstract: A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.

Abstract: A blunt dissector for separating a blood vessel from surrounding tissues in a body comprises a longitudinal rod having a proximal end, a distal end, and an internal passage for conducting insufflation gas between the proximal and distal ends. An interior sleeve is mounted within the longitudinal rod for receiving an endoscope at the proximal end. A transparent tip is mounted to the distal end of the longitudinal rod. A handle is mounted to the proximal end of the longitudinal rod. The longitudinal rod has an outer surface along substantially all of the longitudinal rod between the proximal and distal ends consisting essentially of a fluoropolymer.

Abstract: The body tissue harvesting instrument is provided with a cutter which is disposed at the distal end of an insertion member that is inserted into the body of an organism, and which severs tissue inside the body. The cutter includes: a cutter body which projects from the distal end, and which includes a slit that extends from the distal end toward the base end; a first high-frequency electrode disposed along the two side edges of the slit on the outer surface of the cutter body and a second high-frequency electrode disposed at the base end of the slit; and a mechanism which is disposed on both sides of the distal end of the slit in the projection of the cutter body, which rotates as a result of being pressed by the tissue, and which feeds the tissue toward the interior of the slit. In addition, the parts located on both sides of the distal end of the slit in the projection mutually separate in the thickness direction of the slit.

Abstract: A performance monitor device includes an input unit to input both of address information and event occurrence information, an address mask unit to determine an address area to which each piece of the inputted address information belongs, an execution frequency counter to count a number of times of execution of programs in the address areas, an execution frequency holding unit to hold a counting result of the number of times of execution, an event occurrence information counter to count the event occurrence information corresponding to the address areas having the counting result of the number of times of execution included within a predetermined number of highest ranks, a holding unit to hold a counting results of the event occurrence information, and a storing unit to store the counting result of the event occurrence information corresponding to the address area having the highest number of times of execution in predetermined periods.

Abstract: A harvesting device for an endoscope includes a harvesting member inserted through an outer tube member, including a harvesting portion arranged at the distal end portion of the outer tube member and to perform a harvesting, and configured to move so that the harvesting member moves and positions the harvesting portion at a harvesting position and a standby position, a wipe member inserted through the outer tube member, including a wipe portion arranged at the distal end portion of the outer tube member, and configured to move so that the wipe member moves the wipe portion to wipe a distal end portion of the endoscope, and a conversion mechanism to convert the movement of the harvesting member into that of the wipe member to interlock the wiping of the wipe portion with the positioning of the harvesting portion.

Abstract: A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data.

Abstract: A gas sensor made up of a sensor element and a first and a second hollow cylindrical porcelain insulators covering the sensor element. The first porcelain insulator is laid on the second porcelain insulator in alignment within a body of the gas sensor. A base end surface of the first porcelain insulator is placed in abutment with a top end surface of the second porcelain insulator. At least one of the base end surface of the top end surface has a ground flat area which forms an interface between the first and second porcelain insulators without micro-contacts resulting in concentration of local stress which would lead to breakage of the first or second porcelain insulator when subjected to physical loads.

Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.

Abstract: With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instruction having a possibility of using mutually the same cache line in a cache memory when mutually different cache lines in a main memory are accessed, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated.