Patents by Inventor Seiji Maeda

Seiji Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8171477
    Abstract: An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Patent number: 8145804
    Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 27, 2012
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
  • Publication number: 20120035606
    Abstract: The body tissue harvesting instrument is provided with a cutter which is disposed at the distal end of an insertion member that is inserted into the body to sever tissue inside the body. The cutter includes a slit that extends from the distal end toward the base end; a first high-frequency electrode disposed along the two side edges of the slit on the outer surface of the cutter body and a second high-frequency electrode disposed at the base end of the slit; and a mechanism which is disposed on both sides of the distal end of the slit in the projection of the cutter body which rotates as a result of being pressed by the tissue, and which feeds the tissue toward the interior of the slit. Parts located on both sides of the distal end of the slit in the projection may mutually separate in the thickness direction.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicants: OLYMPUS MEDICAL SYSTEMS CORPORATION, TERUMO CARDIOVASCULAR SYSTEMS CORPORATION
    Inventors: Akihito Kano, Hideyuki Kasahara, Seiji Maeda, Randal J. Kadykowski, Lyne M. Charron-Keller
  • Patent number: 8089014
    Abstract: A waterproof push button switch does not need to be covered with a resin to a height at which a divided connected portion of a case for the switch is hidden by the resin in a height direction and the divided connected portion may be waterproofed. A gap (55, 57) is formed between a peripheral wall portion 7b of a base case 7 and a second cylindrical wall portion 9b of a cover case 9, and between an opposite surface 41 of the cover case 9 and a waterproofing seal member 11. The gap (55, 57) extends from an opening portion of the base case fitting chamber 37 to an annular watertight seal portion 51 to completely surround a periphery of the watertight seal portion 51. The thickness of the gap portion 55 is determined so that the resin entered into the gap portion 55 from an opening portion 37a of the base case fitting chamber 37 reaches the watertight seal portion 51 by surface tension.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: January 3, 2012
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Seiji Maeda, Morio Tada
  • Patent number: 8087020
    Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Publication number: 20110311865
    Abstract: The present invention provides an ionic liquid useful for a lithium secondary battery, which is excellent in performance as an electrolyte material, such that the liquid has ionic conductance and a wide potential window, and is excellent in safety, as well as an electrolyte using the same. The present invention relates to an ionic liquid including a cyanophosphate-based anion represented by the following general formula (1), and an electrolyte using the same, a lithium secondary battery, and a process for producing the ionic liquid. [Chem 1] ?P(CN)nX6-n??(1) (Wherein X is a halogen atom and n is an integer of 1 to 6.
    Type: Application
    Filed: March 16, 2010
    Publication date: December 22, 2011
    Applicant: THE NIPPON SYNTHETIC CHEMICAL INDUSTRY CO., LTD.
    Inventors: Ryouta Tatsumi, Yasuhiro Aoki, Seiji Maeda, Mariko Hori, Seiichirou Hayakawa
  • Patent number: 8048100
    Abstract: A blunt dissector for separating a blood vessel from surrounding tissues in a body comprises a longitudinal rod having a proximal end, a distal end, and an internal passage for conducting insufflation gas between the proximal and distal ends. An interior sleeve is mounted within the longitudinal rod for receiving an endoscope at the proximal end. A transparent tip is mounted to the distal end of the longitudinal rod. A handle is mounted to the proximal end of the longitudinal rod. The longitudinal rod has an outer surface along substantially all of the longitudinal rod between the proximal and distal ends consisting essentially of a fluoropolymer.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Terumo Cardiovascular Systems, Corp.
    Inventors: Randal J. Kadykowski, Lyne M. Charron-Keller, Seiji Maeda, Susumu Komagata, Hideyuki Kasahara, Akihito Kano, Ken Yamatani
  • Patent number: 8037277
    Abstract: A computer-readable storage medium stores a program for causing a processor to perform a process including: acquiring a first address that specifies a start address of a first area on the main memory where a target data to be cached is stored and range information that specifies a size of the first area on the main memory; converting the first address into a second address that specifies a start address of a second area on the local memory, the second area having a one-to-n correspondence (n=positive integer) to a part of a bit string of the first address; copying the target data stored in the first area specified by the first address and the range information onto the second area specified by the second address and the range information; and storing the second address to allow accessing the target data copied onto the local memory.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota, Kazuya Kitsunai
  • Publication number: 20110230881
    Abstract: An endoscopic surgical instrument includes an insertion section which is inserted into a body cavity, and a surgical section which is disposed on a tip of the insertion section and treats an object. The surgical section includes a body section, and a first electrode, a second electrode, and a third electrode which are disposed on the body section. The surgical section coagulates and cuts the object by using a combination of not less than two of the first electrode, the second electrode, and the third electrode.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 22, 2011
    Inventors: Seiji Maeda, Hideyuki Kasahara, Ken Yamatani, Akihito Kano, Randal James Kadykowski, Lyne Madeleine Charron-Keller
  • Publication number: 20110231593
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Application
    Filed: December 1, 2010
    Publication date: September 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta YASUFUKU, Shigeaki IWASA, Yasuhiko KUROSAWA, Hiroo HAYASHI, Seiji MAEDA, Mitsuo SAITO
  • Publication number: 20110174615
    Abstract: A deterioration signal generation device for an oxygen sensor having a power supply different than a power supply connected to an external device, including a connection unit for electrically connecting the ground lines of the respective power supplies; a first acquisition unit for electrically connecting to a first output line at a reference potential side and to a second output line at a sensor potential side of the oxygen sensor, to obtain first and second potentials, respectively; an operation unit that calculates a first differential value between the first and second potentials; a processing unit that performs an operation on the first differential value; a second acquisition unit that acquires a third potential of a first input line at a reference potential side of the external device; and an output unit that generates the deterioration signal by superposing the second differential value on the third potential.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 21, 2011
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventor: Seiji MAEDA
  • Publication number: 20110161624
    Abstract: Mechanisms are provided for performing a floating point collect and operate for a summation across a vector for a dot product operation. A routing network placed before the single instruction multiple data (SIMD) unit allows the SIMD unit to perform a summation across a vector with a single stage of adders. The routing network routes the vector elements to the adders in a first cycle. The SIMD unit stores the results of the adders into a results vector register. The routing network routes the summation results from the results vector register to the adders in a second cycle. The SIMD unit then stores the results from the second cycle in the results vector register.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian K. Flachs, Seiji Maeda, Steven Osman
  • Patent number: 7957933
    Abstract: An information processing apparatus includes a receptor for receiving an event signal occurring in hardware during program execution in time series, a feature event counter for counting the number of occurrences of a feature event to determine the feature of the program, a stored event counter for counting the number of occurrences of stored event determined from the feature event with the maximum number of occurrences, and a storage for storing the count result of the number of occurrences of the stored event.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: June 7, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kitsunai, Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota
  • Publication number: 20110104482
    Abstract: A polyurethane adhesive for outdoor use that uses a base material and a curing agent, wherein the base material comprises a polyol (A) composed of a polyester polyol and/or polyester polyurethane polyol containing a dibasic acid component comprising 40 to 80 mol % of an aromatic dibasic acid and 20 to 60 mol % of an aliphatic dibasic acid having 9 or more carbon atoms, and a polyhydric alcohol component comprising 20 to 100 mol % of an aliphatic polyhydric alcohol having 5 or more carbon atoms, and the curing agent comprises a polyisocyanate (B) containing an isocyanurate in a weight ratio of 50 to 100%.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 5, 2011
    Applicant: TOYO INK MFG. CO., LTD.,
    Inventors: Bungo Yasui, Seiji Maeda, Hiroki Sugi, Kenshiro Shimada
  • Publication number: 20110099336
    Abstract: A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters.
    Type: Application
    Filed: September 15, 2010
    Publication date: April 28, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenta YASUFUKU, Seiji Maeda
  • Publication number: 20110072170
    Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
  • Patent number: 7913256
    Abstract: A real-time system includes a plurality of processors for executing jobs of a plurality of periodic tasks each having predetermined period, assigns each job in a period of each of the tasks to the processors, calculates distribution of execution times during which jobs assigned are executed on the processors, determines, based on the distribution, whether each of the jobs finishes by a deadline within the period, determines that scheduling is impossible, when one of the jobs is determined not to finish by the deadline, determines whether the distribution of the execution times of the jobs each determined to finish by the deadline converge, and determines that scheduling is possible, when the distribution converge.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Torii, Seiji Maeda
  • Publication number: 20110055647
    Abstract: A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Maeda, Kenta Yasufuku
  • Publication number: 20110023277
    Abstract: A large-diameter-side end surface (104a) of a cotter (104) can be supported by a cotter holder (32) from below through inserting a shaft member (102) along an inner periphery of the cotter (104) from above the cotter (104). In this state, a protrusion (104b) of the cotter (104) and an annular groove (102a) of the shaft member (102) are fitted to each other, and the cotter (104) and a retainer (103) are taper-fitted to each other. Consequently, the cotter is prevented from being unstable, and hence it is possible to assemble the retainer (103) and the cotter (104) to the shaft member (102) with good accuracy.
    Type: Application
    Filed: January 14, 2009
    Publication date: February 3, 2011
    Inventors: Yoshiaki Takagi, Seiji Maeda
  • Patent number: 7877751
    Abstract: According to an aspect of the present invention, heat emissions of processors are level among the processors, and it is possible to suppress occurrence of stop of process due to overheating. The control IC assigns tasks to the processors, and thereafter rectifies an assignment result such that temperatures of the processors become almost level among the processors, on the basis of the temperatures of the processors obtained by temperature sensors. This structure enables level heat emissions among the processors, and suppresses occurrence of stop of process due to overheating.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Maeda, Tatsunori Kanai