Patents by Inventor Seiji Miura
Seiji Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6928512Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.Type: GrantFiled: June 6, 2002Date of Patent: August 9, 2005Assignees: Hitachi ULSI Systems Co, Ltd., Renesas Technology CorporationInventors: Kazushige Ayukawa, Seiji Miura, Tetsuya Iwamura, Kouichi Hoshi, Yoshikazu Saitou
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Publication number: 20050128853Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: January 19, 2005Publication date: June 16, 2005Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Publication number: 20050099876Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 14, 2004Publication date: May 12, 2005Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20050092584Abstract: A parts aligner is provided with an attraction means 8 orbitally movable in a specific orbit R, and also provided with a posture shift guide 11, a regulating piece 12 and a thickness sorting guide 13 along a specific circumference P corresponding to the specific orbit R in the order of the direction of orbital movement of the attraction means 8. With this structure, only regular parts shifted into a specific posture are guided to an alignment and feed guide 14 and irregular parts are stored in an irregular parts storing part 16.Type: ApplicationFiled: June 28, 2004Publication date: May 5, 2005Applicant: Seki Kogyo Co., Ltd.Inventors: Kouji Sakota, Masaaki Miura, Seiji Miura
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Publication number: 20050056683Abstract: The forward movement of a feed rod 15 of a nut feeder permits pressurization of air in an air chamber 3a defined in a rod holder 3, thereby blowing the air out of the air outlet 20 through an air inlet 21 and an air passage 22. A nut 7 is held on the feed rod 15 by the pressure of the air blow from the air outlet 20.Type: ApplicationFiled: June 30, 2004Publication date: March 17, 2005Applicant: Seki Kogyo Co., Ltd.Inventors: Masaaki Miura, Kouji Sakota, Seiji Miura
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Patent number: 6847575Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: April 11, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6847578Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 9, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040223366Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: June 7, 2004Publication date: November 11, 2004Applicant: Renesas Technology Corp.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20040189259Abstract: A battery pack with a charge control function includes a charge protection circuit and a charge control circuit. The charge control circuit turns a discharge control switch on or off to control a discharge current which flows from a secondary battery to a load and also turns a charge control switch on or off to control a charge current which flows from a charger to the secondary battery. When an abnormal voltage is input, the charge control circuit turns the charge control switch on or off to stop the charging of the secondary battery through the charger.Type: ApplicationFiled: February 26, 2004Publication date: September 30, 2004Applicant: Mitsumi Electric Co. Ltd.Inventors: Seiji Miura, Yukihiro Terada, Akira Ikeuchi
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Patent number: 6791877Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: June 10, 2002Date of Patent: September 14, 2004Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20040114451Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 9, 2003Publication date: June 17, 2004Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040095818Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: November 14, 2003Publication date: May 20, 2004Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6708249Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: March 20, 2002Date of Patent: March 16, 2004Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040049629Abstract: A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.Type: ApplicationFiled: May 28, 2003Publication date: March 11, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Seiji Miura, Kazushige Ayukawa, Tetsuya Iwamura
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Patent number: 6675269Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: February 4, 2003Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20030206478Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: April 11, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Publication number: 20030158789Abstract: A viewer apparatus, content providing apparatus, advertisement providing apparatus, and electronic merchandise distribution system are connected to a network apparatus. Upon receiving excellent content information evaluated/analyzed by a content evaluation apparatus in accordance with a content buying request, a content buying apparatus in the distribution system transmits order data to the content providing apparatus, makes a content buying contract from replay data, and transmits a content and content information to a distribution apparatus. The distribution apparatus generates advertising space information from the content information, presents the advertising space information to the advertisement providing apparatus through an advertisement acquisition processing apparatus, and acquires advertising space sales, an advertising content, and advertising content information.Type: ApplicationFiled: February 14, 2003Publication date: August 21, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Seiji Miura, Arata Ando, Akihiro Nonoyama
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Publication number: 20030126392Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: February 4, 2003Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6587934Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: August 20, 2001Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6587393Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: May 9, 2002Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou