Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: In a drainage pump station, a driving machine has a capacity greater than a shaft power necessary for no-discharge operation of a pump, and during severe flooding the pump is operated at an overload exceeding its design capacity. During maintenance operation water is fed from a river on the delivery side of the pump station into the station. When an inflow of rainwater into the pump station is great the pump is operated at the necessary capacity, when it becomes small the water level is kept above a rated value, and when the inflow rate is zero the pump discharge is increased to a capacity at which sediment can be discharged. A suction blower is disposed at the top of a suction sump and interstage valves are disposed in entrances of vertical shafts to effect efficient ventilation of the underground waterway. A feed channel is operated as a pressure channel and the pump is of variable capacity and the water level in the underground waterway is controlled to be constant.