Patents by Inventor Seiji Nakahata

Seiji Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130244406
    Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
    Type: Application
    Filed: February 26, 2013
    Publication date: September 19, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoshi KASAI, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8524575
    Abstract: A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 10p and 10q having a main plane from a group III nitride bulk crystal 1, the main planes 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20-21}, {20-2-1}, {22-41}, and {22-4-1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the main planes 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a group III nitride crystal 20 on the main planes 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 8501592
    Abstract: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm?2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality of low-dislocation-density regions (20k) in which the dislocation density is lower than that of the high-dislocation-density regions (20h), wherein the average dislocation density is not greater than 5×105 cm?2. Herein, the ratio of the dislocation density of the high-dislocation-density region(s) (20h) to the average dislocation density is sufficiently large to check the propagation of cracks in the substrate. And the semiconductor device manufacturing method utilizes the freestanding III-nitride single crystal substrate (20p).
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Seiji Nakahata
  • Patent number: 8476158
    Abstract: A GaN substrate storage method of storing, within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m3, a GaN substrate (1) having a planar first principal face (1m), and whose plane orientation in an arbitrary point (P) along the first principal face (1m) and separated 3 mm or more from the outer edge thereof has an off-inclination angle ?? of ?10° or more, 10° or less with respect to the plane orientation of an arbitrarily designated crystalline plane (1a) that is inclined 50° or more, 90° or less with respect to a plane (1c), being either the (0001) plane or the (000 1) plane, through the arbitrary point. In this way a method of storing GaN substrates whose principal-face plane orientation is other than (0001) or (000 1), with which semiconductor devices of favorable properties can be manufactured is made available.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 2, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 8421190
    Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: April 16, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takuji Okahisa, Hideaki Nakahata, Seiji Nakahata
  • Patent number: 8404042
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8404569
    Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8377204
    Abstract: Affords methods of growing III nitride single crystals of favorable crystallinity with excellent reproducibility, and the III nitride crystals obtained by the growth methods. One method grows a III nitride single crystal (3) inside a crystal-growth vessel (11), the method being characterized in that a porous body formed from a metal carbide, whose porosity is between 0.1% and 70% is employed in at least a portion of the crystal-growth vessel (11). Employing the crystal-growth vessel (11) makes it possible to discharge from 1% to 50% of a source gas (4) inside the crystal-growth vessel (11) via the pores in the porous body to the outside of the crystal-growth vessel (11).
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: February 19, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Shinsuke Fujiwara, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 8362521
    Abstract: Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: January 29, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Hideaki Nakahata, Koji Uematsu, Makoto Kiyama, Youichi Nagai, Takao Nakamura
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Publication number: 20120329245
    Abstract: A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 10p and 10q having a main plane from a group III nitride bulk crystal 1, the main planes 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20-21}, {20-2-1}, {22-41}, and {22-4-1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the main planes 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a group III nitride crystal 20 on the main planes 10pm and 10qm of the substrates 10p and 10q.
    Type: Application
    Filed: December 28, 2011
    Publication date: December 27, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Publication number: 20120315445
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Application
    Filed: August 2, 2012
    Publication date: December 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20120305933
    Abstract: A group III nitride semiconductor light-emitting device includes a GaN crystal substrate and at least one group III nitride semiconductor layer disposed on a main surface of the GaN crystal substrate. The substrate includes a matrix crystal region and a c-axis-inverted crystal region. An off angle ? is formed between the main surface and a {0001} plane, and an off-angle component of a first direction has an absolute value |?1| of 0.03° or more and 1.1° or less and an off-angle component of a second direction has an absolute value |?2 of 0.75×|?1| or less, where the first direction is one of <10-10> and <1-210> directions and the second direction is the other thereof. Accordingly, the group III nitride semiconductor light-emitting device with excellent characteristics including the group III nitride semiconductor layer having good morphology and uniform physical properties and formed on the GaN crystal substrate is obtained.
    Type: Application
    Filed: March 12, 2012
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji NAKAHATA, Fumitake NAKANISHI
  • Patent number: 8304334
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: November 6, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8294245
    Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Nakahata, Shinsuke Fujiwara, Takashi Sakurada, Yoshiyuki Yamamoto, Seiji Nakahata, Tomoki Uemura
  • Patent number: 8283694
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 9, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8253162
    Abstract: The present GaN substrate can have an absorption coefficient not lower than 7 cm?1 for light having a wavelength of 380 nm and light having a wavelength of 1500 nm, an absorption coefficient lower than 7 cm?1 for at least light having a wavelength not shorter than 500 nm and not longer than 780 nm, and specific resistance not higher than 0.02 ?cm. Here, the absorption coefficient for light having a wavelength not shorter than 500 nm and not longer than 780 nm can be lower than 7 cm?1. Thus, a GaN substrate having a low absorption coefficient for light having a wavelength within a light emission wavelength region of a light-emitting device and specific resistance not higher than a prescribed value and being suitable for the light-emitting device is provided.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 28, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Toshihiro Kotani, Fumitake Nakanishi, Seiji Nakahata, Koji Uematsu
  • Patent number: 8227826
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 8198177
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: June 12, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu