Patents by Inventor Seiji Nakahata

Seiji Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120142168
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
    Type: Application
    Filed: February 7, 2012
    Publication date: June 7, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 8192543
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: June 5, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20120126371
    Abstract: A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 ?m and arranged at a spacing of 250 to 10,000 ?m; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 ?cm?r?0.01 ?cm, a thickness of 100 ?m or more, and a radius of bow curvature U of 3.5 m?U?8 m.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 24, 2012
    Inventors: Fumitaka Sato, Seiji Nakahata, Makoto Kiyama
  • Publication number: 20120118226
    Abstract: Fracture toughness of AlGaN single-crystal substrate is improved and its absorption coefficient reduced. A nitride semiconductor single-crystal substrate has a composition represented by the formula AlxGa1-xN (0?x?1), and is characterized by having a fracture toughness of (1.2?0.7x) MPa•m1/2 or greater and a surface area of 20 cm2, or, if the substrate has a composition represented by the formula AlxGa1-xN (0.5?x?1), by having an absorption coefficient of 50 cm?1 or less in a 350 to 780 nm total wavelength range.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 17, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Seiji NAKAHATA
  • Publication number: 20120094473
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Inventors: Keiji ISHIBASHI, Akihiro HACHIGO, Masato IRIKURA, Seiji NAKAHATA
  • Publication number: 20120070962
    Abstract: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm?2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality of low-dislocation-density regions (20k) in which the dislocation density is lower than that of the high-dislocation-density regions (20h), wherein the average dislocation density is not greater than 5×105 cm?2. Herein, the ratio of the dislocation density of the high-dislocation-density region(s) (20h) to the average dislocation density is sufficiently large to check the propagation of cracks in the substrate. And the semiconductor device manufacturing method utilizes the freestanding III-nitride single crystal substrate (20p).
    Type: Application
    Filed: January 14, 2011
    Publication date: March 22, 2012
    Inventors: Shinsuke Fujiwara, Seiji Nakahata
  • Patent number: 8134223
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 13, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20120040511
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji NAKAHATA, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
  • Publication number: 20120034763
    Abstract: The present invention provides a method of manufacturing a nitride semiconductor substrate capable of efficiently manufacturing a nitride semiconductor substrate having a nonpolar plane as a major surface in which polycrystalline growth is minimized. A method of manufacturing a GaN substrate, which is a nitride semiconductor substrate, includes steps (S10 and S20) of preparing a starting substrate composed of GaN and having a major surface with an off-axis angle of between 4.1° and 47.8° inclusive with respect to a {1-100} plane, a step (S40) of epitaxially growing a semiconductor layer made of GaN on the major surface of the starting substrate, and a step (S50) of picking out a GaN substrate having an m plane as the major surface from the semiconductor layer.
    Type: Application
    Filed: October 14, 2011
    Publication date: February 9, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki Osada, Koji Uematsu, Seiji Nakahata, Fumitake Nakanishi
  • Patent number: 8110484
    Abstract: A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 ?m and arranged at a spacing of 250 to 10,000 ?m; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 ?cm?r?0.01 ?cm, a thickness of 100 ?m or more, and a radius of bow curvature U of 3.5 m?U?8 m.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: February 7, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata, Makoto Kiyama
  • Patent number: 8101968
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Patent number: 8067300
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 29, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
  • Publication number: 20110278588
    Abstract: A GaN substrate storage method of storing, within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m3, a GaN substrate (1) having a planar first principal face (1m), and whose plane orientation in an arbitrary point (P) along the first principal face (1m) and separated 3 mm or more from the outer edge thereof has an off-inclination angle ?? of ?10° or more, 10° or less with respect to the plane orientation of an arbitrarily designated crystalline plane (1a) that is inclined 50° or more, 90° or less with respect to a plane (1c), being either the (0001) plane or the (000 1) plane, through the arbitrary point. In this way a method of storing GaN substrates whose principal-face plane orientation is other than (0001) or (000 1), with which semiconductor devices of favorable properties can be manufactured is made available.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 17, 2011
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 8038794
    Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: October 18, 2011
    Assignees: Sumitomo Electric Industries, Ltd.
    Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
  • Publication number: 20110223749
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Application
    Filed: October 27, 2010
    Publication date: September 15, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiromu SHIOMI, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 8008173
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: August 30, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Seiji Nakahata
  • Patent number: 8002892
    Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: August 23, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
  • Publication number: 20110133207
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110133209
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji ISHIBASHI, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110121311
    Abstract: The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 26, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Fumitaka SATO, Akihiro HACHIGO, Naoki MATSUMOTO, Yoko MAEDA, Seiji NAKAHATA