Patents by Inventor Seiji Nakahata

Seiji Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110108852
    Abstract: The present GaN substrate can have an absorption coefficient not lower than 7 cm?1 for light having a wavelength of 380 nm and light having a wavelength of 1500 nm, an absorption coefficient lower than 7 cm?1 for at least light having a wavelength not shorter than 500 nm and not longer than 780 nm, and specific resistance not higher than 0.02 ?cm. Here, the absorption coefficient for light having a wavelength not shorter than 500 nm and not longer than 780 nm can be lower than 7 cm?1. Thus, a GaN substrate having a low absorption coefficient for light having a wavelength within a light emission wavelength region of a light-emitting device and specific resistance not higher than a prescribed value and being suitable for the light-emitting device is provided.
    Type: Application
    Filed: December 30, 2010
    Publication date: May 12, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Toshihiro Kotani, Fumitake Nakanishi, Seiji Nakahata, Koji Uematsu
  • Patent number: 7915149
    Abstract: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106 ?·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: March 29, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Fumitaka Sato, Yoshiki Miura, Akinori Koukitu, Yoshinao Kumagai
  • Publication number: 20110065265
    Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoshi KASAI, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 7905958
    Abstract: A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 15, 2011
    Assignees: Sumitomo Electric Industries, Ltd.
    Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
  • Publication number: 20110057197
    Abstract: A GaN single crystal substrate has a main surface with an area of not less than 10 cm2, the main surface has a plane orientation inclined by not less than 65° and not more than 85° with respect to one of a (0001) plane and a (000-1) plane, and the substrate has at least one of a substantially uniform distribution of a carrier concentration in the main surface, a substantially uniform distribution of a dislocation density in the main surface, and a photoelasticity distortion value of not more than 5×10?5, the photoelasticity distortion value being measured by photoelasticity at an arbitrary point in the main surface when light is applied perpendicularly to the main surface at an ambient temperature of 25° C. Thus, the GaN single crystal substrate suitable for manufacture of a GaN-based semiconductor device having a small variation of characteristics can be obtained.
    Type: Application
    Filed: June 17, 2010
    Publication date: March 10, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Koji Uematsu, Hideki Osada, Seiji Nakahata
  • Patent number: 7901960
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid, material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110018003
    Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.
    Type: Application
    Filed: October 7, 2010
    Publication date: January 27, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuji OKAHISA, Hideaki Nakahata, Seiji Nakahata
  • Patent number: 7863167
    Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 4, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Publication number: 20100326876
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Application
    Filed: September 7, 2010
    Publication date: December 30, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 7858502
    Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: December 28, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20100322841
    Abstract: Affords Group-III nitride single-crystal ingots and III-nitride single-crystal substrates manufactured utilizing the ingots, as well as methods of manufacturing III-nitride single-crystal ingots and methods of manufacturing III-nitride single-crystal substrates, wherein the incidence of cracking during length-extending growth is reduced. Characterized by including a step of etching the edge surface of a base substrate, and a step of epitaxially growing onto the base substrate hexagonal-system III-nitride monocrystal having crystallographic planes on its side surfaces. In order to reduce occurrences of cracking during length-extending growth of the ingot, depositing-out of polycrystal and out-of-plane oriented crystal onto the periphery of the monocrystal must be controlled.
    Type: Application
    Filed: December 24, 2008
    Publication date: December 23, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuji Okahisa, Seiji Nakahata, Tomoki Uemura
  • Patent number: 7854804
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1-d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: December 21, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20100314625
    Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 16, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideaki NAKAHATA, Shinsuke FUJIWARA, Takashi SAKURADA, Yoshiyuki YAMAMOTO, Seiji NAKAHATA, Tomoki UEMURA
  • Patent number: 7851381
    Abstract: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least ?850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura, Masato Irikura, Seiji Nakahata
  • Publication number: 20100297790
    Abstract: The present invention provides a method for producing semiconductor devices by which the fraction defective upon division into chips is reduced and the yield is enhanced. A method for producing semiconductor devices according to the present invention includes a dislocation-density evaluation step of measuring a dislocation density of sections of GaN substrates, the sections intersecting with principal surfaces of the GaN substrates, and selecting a GaN substrate in which the dislocation density is a predetermined value or less; and a division step of, after a functional device portion is epitaxially grown on the GaN substrate having been selected in the dislocation-density evaluation step, dividing the GaN substrate into chip-shaped parts.
    Type: Application
    Filed: December 12, 2008
    Publication date: November 25, 2010
    Inventors: Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 7834423
    Abstract: AlxInyGa1-x-yN (0?x?1; 0?x?1; 0?x+y?1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0?x?1; 0?y?1; 0?x+y?1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Hideaki Nakahata
  • Publication number: 20100275836
    Abstract: The present method for growing group III nitride crystal includes the steps of: preparing a substrate including group III nitride seed crystal constituting one main surface thereof; forming a plurality of facets on the main surface of the substrate through vapor phase etching; and growing group III nitride crystal on the main surface on which the facets are formed. In this way, group III nitride crystal having a low dislocation density can be obtained readily and efficiently.
    Type: Application
    Filed: January 8, 2009
    Publication date: November 4, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Patent number: 7816238
    Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: October 19, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Osada, Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Takashi Kyono, Katsushi Akita, Yoshiki Miura
  • Patent number: 7811908
    Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: October 12, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideyuki Ijiri, Seiji Nakahata
  • Patent number: 7794543
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: September 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata