Abstract: A target positioning device and method based on a plecotus auritus double-pinna bionic sonar. An echo positioning device based on bionic pinnae of a bat can determine an azimuth and an elevation of a target to locate the spatial location of the target by using echoes obtained by two array elements, resolving a problem that two array element antennas cannot locate the space coordinates. In a positioning method based on bionic pinnae of a bat according to filtering characteristics of bat ears, a method for estimating a spatial location by a neural network is used, and a pulse string estimation method is used to reduce the error of estimated angles, to obtain a precise azimuth and elevation.

Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Abstract: This application relates to the field of cloud computing, and specifically, to a method for providing an edge service for a terminal by using a resource of an edge resource cluster in a cloud computing system. The cloud computing system includes a central resource cluster and at least one edge resource cluster. The method includes: a management node deployed in the central resource cluster determines a target execution node based on an edge service application range that is specified by a tenant or that is determined by the management node based on information about a tenant; the target execution node determines, according to an edge service policy sent by the management node, a target edge node from at least one edge node deployed in the at least one edge resource cluster; and the target execution node further forwards an edge service request to the target edge node.

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

Abstract: A communication method, a communications apparatus, and a storage medium are disclosed, to reduce a probability that consecutive bit errors occur in a communications system. A received to-be-sent signal is modulated to obtain a modulated signal, and N rounds of operations are further performed on the modulated signal to obtain an encoded signal. An output of the 1st-round operation in the N rounds of operations is determined based on the modulated signal and an output that is of the Nth-round operation and that is processed by a first delay circuit, and an output of the ith-round operation in the N rounds of operations is determined based on an output of the (i?1)th-round operation and an output that is of the Nth-round operation and that is processed by a second delay circuit, where i is an integer greater than 1 and less than or equal to N.

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

Abstract: The present disclosure relates to a method and apparatus for a file system, the file system comprising at least a first logical storage area and a second logical storage area, a logical block of the first logical storage area and that of the second logical storage area being different in size, and in response to a request for creating a file, selecting a logical storage area for storing the file from the at least first logical storage area and second logical storage area; and storing the file in the selected logical storage area. According to the above various embodiments of the present invention, a direct and effective way may be used to support variable-length block size in a file system, without increasing metadata and positioning overheads.

Abstract: A method for inhibiting extension of an ocular axis, wherein the extension of the ocular axis is inhibited by a manner of increasing the volume of choroidal blood flow. The method may include expanding choroidal vessels by using drugs, including locally administering a drug increasing the volume of choroidal blood flow to an eye.

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

Abstract: A chuck configured to be operably coupled to a power driver having a rotatable drive spindle is provided. The chuck (100) may include a body (130) having a center axis (50) and a plurality of clamping jaws (101) configured to clamp onto a working bit. The clamping jaws (101) may be configured to angularly translate relative to the center axis towards or away from a clamping jaw point of convergence (154) to close or open a working bit opening defined by the clamping jaws (101). The clamping jaw point of convergence (154) may be on the center axis. The chuck (100) may also include a plurality of bit alignment jaws (150). The bit alignment jaws (150) may be configured to maintain the working bit within the working bit opening by being configured translate towards or away from a bit alignment jaw point of convergence (153) that is on the center axis (50) and disposed rearward of the clamping jaw point of convergence (154).

Abstract: Computer software and a system are disclosed to provide group control and network operations to/for a multiplicity of distributed energy storage units. The group control software and system can connect multiple individual distributed energy storage units and operate those units in synchronicity to create a large virtual energy storage device. Methods of controlling the distributed energy storage units include: a browser-based online user portal, or network-based, system-to-system protocols by third-party operation controllers.

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

Abstract: A spraying apparatus and control method therefor and a dishwasher. The spraying apparatus comprises: a spray pipe, a water injection spray pipe being provided on the spray pipe; a drive mechanism, the drive mechanism comprising a driving gear and multiple driven gears engaging with the driving gear, and the driven gear being connected to the spray pipe to drive the spray pipe to rotate; a drive mechanism, the drive mechanism being connected to the driving gear to drive the driving gear to rotate.

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

Abstract: A chuck configured to be operably coupled to a power driver having a rotatable drive spindle is provided. The chuck (100) may include a body (130) having a center axis (50) and a plurality of clamping jaws (101) configured to clamp onto a working bit. The clamping jaws (101) may be configured to angularly translate relative to the center axis towards or away from a clamping jaw point of convergence (154) to close or open a working bit opening defined by the clamping jaws (101). The clamping jaw point of convergence (154) may be on the center axis. The chuck (100) may also include a plurality of bit alignment jaws (150). The bit alignment jaws (150) may be configured to maintain the working bit within the working bit opening by being configured translate towards or away from a bit alignment jaw point of convergence (153) that is on the center axis (50) and disposed rearward of the clamping jaw point of convergence (154).

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.