Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

Abstract: A method for incremental upgrade is provided. The method is used in a device and includes: receiving an incremental update package corresponding to an application, wherein the incremental update package at least includes an incremental and differential file and the size of a target-version file; obtaining idle resource of a memory in the device and a current-version file corresponding to the application; comparing the idle resource of the memory with a maximum upgrade resource requirement to choose an upgrade process for upgrading the application, wherein the maximum upgrade resource requirement is a capacity sum of the size of the current-version file, the size of the incremental and differential file, and the size of the target-version file; and restoring the target-version file according to the upgrade process, and installing the target-version file.

Abstract: Embodiments of the present disclosure relate to a method and device for migrating data. The method comprises identifying cold data in a primary storage system. The method further comprises, in response to determining that the cold data is in a non-compression state, obtaining the cold data from the primary storage system via a first interface, the first interface being configured for a user to access the primary storage system. The method further comprises obtaining, in response to determining the cold data is in a compression state, the cold data in the compression state from the primary storage system via a second interface that is different from the first interface. The method further comprises migrating the obtained cold data from the primary storage system to a secondary storage system.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A hybrid power system, includes at least one first isolation transformer having an input configured to be connectable to an output of a power supply; an energy storage system having at least one energy storage device and a power conversion system having at least one DC-to-AC converter connected to the at least one energy storage device; and at least one second isolation transformer configured as a step-up isolation transformer having an input connected to an output of the storage system.

Abstract: A target positioning device and method based on a plecotus auritus double-pinna bionic sonar. An echo positioning device based on bionic pinnae of a bat can determine an azimuth and an elevation of a target to locate the spatial location of the target by using echoes obtained by two array elements, resolving a problem that two array element antennas cannot locate the space coordinates. In a positioning method based on bionic pinnae of a bat according to filtering characteristics of bat ears, a method for estimating a spatial location by a neural network is used, and a pulse string estimation method is used to reduce the error of estimated angles, to obtain a precise azimuth and elevation.

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

Abstract: A signal generation method and an electronic device pertain to the field of communications technologies, and include normalizing an I path of four-level signals and a Q path of four-level signals to obtain a normalized I path of four-level signals and a normalized Q path of four-level signals, mapping the normalized I path of four-level signals and the normalized Q path of four-level signals based on a normalization coefficient to obtain two paths of six-level signals, and driving a dual-drive Mach-Zehnder modulator (DDMZM) based on the six-level signals.

Abstract: This application discloses a flexible Ethernet group establishment method and a device. The method includes: determining that there are at least M physical layer PHY links; receiving at least M delay test requests sent by a near-end device; determining, by the far-end device, at least M receiving time points at which the at least M delay test requests are received; and determining M PHY links used to establish a flexible Ethernet group, from the at least M PHY links based on the at least M receiving time points, where a delay difference between any two of the M PHY links satisfies a preset delay condition. According to the method in this application, the delay difference between the any two PHY links is accurately determined based on time points at which delay test requests are received over any two PHY links.

Abstract: The invention discloses a preparation method of a polyimide film having a low dielectric constant and high fracture toughness; in the method an aromatic diamine solution is firstly prepared, and then a poly(5-norbornene-2,3-dicarboxylic anhydride-alt-maleimide isobutyl polyhedral oligomeric silsesquioxane) and aromatic dianhydride are ground, uniformly mixed, added to the aromatic diamine solution, and stirred to obtain a poly(5-norbornene-2,3-dicarboxylic anhydride-alt-maleimide isobutyl polyhedral oligomeric silsesquioxane)/polyamic acid solution; the solution is uniformly applied on a clean glass sheet, then placed in a vacuum drying oven, cooled to room temperature, and then a film is peeled off in water by ultrasonic and dried under vacuum to obtain the desired product. The dielectric constant of the film obtained by the invention is reduced to 2.

Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

Abstract: A computer implemented method at an energy management system (EMS) controller apparatus for automatic generation of a SCADA (supervisory control and data acquisition) slave interface for an energy management system (EMS), includes storing a SCADA configuration file mapping SCADA data points to EMS data objects; providing the EMS data objects coded in statically typed programming language; providing site configuration information of the energy management system (EMS); scanning, by an object access framework (OAF), EMS data objects with EMS annotations and combining them with the site configuration information to generate an object binding repository (OBR); and compiling the SCADA configuration file to combine the SCADA data points mapping with the object binding repository to generate SCADA bindings information as part of the SCADA slave interface for the energy management system (EMS).

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

Abstract: The present invention discloses a leveling device for adjusting an installation gap between a first component and a second component. The first component and the second component respectively have a cooperative installation surface, the cooperative installation surface of the first component is provided with at least one leveling device; the leveling device comprises a driving device installed in the cooperative installation surface of the first component and an adjustment head rotatably connected to the driving device, the adjustment head moves upwardly or retracts downwardly relative to the cooperative installation surface of the first component; the driving device drives the adjustment head to protrude outside an installation position thereof and abut with the second component located on an opposite side of the installation position of the adjustment head to adjust the gap between the first and second component. The present invention relates to an easy-to-level display screen using the leveling device.

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.