Patents by Inventor Seng Tan

Seng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991938
    Abstract: A memory device may be provided, including a first electrode, an insulating element arranged over the first electrode, a second electrode arranged over the insulating element, a switching layer and a conductive line electrically coupled to the second electrode. Each of the first electrode, the insulating element, and the second electrode may include a first side surface and a second side surface. Centers of the first electrode, the insulating element, and the second electrode may be substantially vertically aligned. The first side surface and the second side surface of the second electrode may be substantially vertically aligned with the first side surface and the second side surface of at least one of the insulating element and the first electrode. The switching layer may be conformal to the first side surfaces and the second side surfaces of the second electrode and the insulating element.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 21, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • Publication number: 20240162147
    Abstract: Structures for an electronic fuse and methods of forming an electronic fuse. The structure comprises an electronic fuse including a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The first terminal, the second terminal, and the fuse link each include a semiconductor layer and a silicide layer. The silicide layer includes a first portion on the first terminal, a second portion on the second terminal, and a third portion on the fuse link. The fuse link includes an airgap between the semiconductor layer and the third portion of the silicide layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Inventors: Shyue Seng Tan, Zar Lwin Zin, Eng Huat Toh
  • Patent number: 11975477
    Abstract: The invention generally relates to shape memory films that are tri-functionally crosslinked and that comprise multiple, non-terminal, phenylethynyl moieties. In addition, the present invention relates methods of fabricating such films. Due to the improved properties of such SMPs, the SMP designer can program in to the SMP thermomechanical property enhancements that make the SMP suitable, among other things, for advanced sensors, high temperature actuators, responder matrix materials and heat responsive packaging.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 7, 2024
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Loon-Seng Tan, David H. Wang, Zhenning Yu
  • Patent number: 11976231
    Abstract: A family of low-molecular-weight, main-chain thermotropic liquid-crystalline co-polyimides (TLC-CoPI) that are crosslinkable, and based on a unique, liquid-crystallinity (LC)-enabling diamine, namely, 1,3-bis[4-(4?-aminophenoxy)cumyl]benzene (BACB) and two or more mesogenic dianhydrides, at least one of which is a diphthalic dianhydride (DPA) that contains one or more thermally reactive and crosslinkable moieties similar to that of phenylethynyl (PE) is disclosed. Processes of making and using such low-molecular-weight, main-chain thermotropic liquid-crystalline co-polyimides are also provided.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: May 7, 2024
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Loon-Seng Tan, Zhenning Yu, Bingqian Zheng, Hilmar Koerner
  • Publication number: 20240136395
    Abstract: Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik
  • Publication number: 20240128163
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20240124652
    Abstract: A family of low-molecular-weight, main-chain thermotropic liquid-crystalline polyimides (TLC-PI) that are crosslinkable is disclosed. These all-aromatic TLC-PI are derived from (i) wholly aromatic and flexible diamine monomers, in which the linkage between the two aniline-ends contains a relatively high heat-tolerant but flexible chain constituted by two or more units of 1,4-phenoxy or 1,3-phenoxy or in combinations of both. Processes of making and using such all-aromatic TLC-PI is also provided.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 18, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu, Bingqian Zheng, Hilmar Koerner
  • Publication number: 20240110098
    Abstract: A family of low-molecular-weight, main-chain thermotropic liquid-crystalline co-polyimides (TLC-CoPI) that are crosslinkable, and based on a unique, liquid-crystallinity (LC)-enabling diamine, namely, 1,3-bis[4-(4?-aminophenoxy)cumyl]benzene (BACB) and two or more mesogenic dianhydrides, at least one of which is a diphthalic dianhydride (DPA) that contains one or more thermally reactive and crosslinkable moieties similar to that of phenylethynyl (PE) is disclosed. Processes of making and using such low-molecular-weight, main-chain thermotropic liquid-crystalline co-polyimides are also provided.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 4, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu, Bingqian Zheng, Hilmar Koerner
  • Publication number: 20240109837
    Abstract: A family of low-molecular-weight, main-chain thermotropic liquid-crystalline polyimides (TLC-PI) that are crosslinkable is disclosed. These all-aromatic TLC-PI are derived from (i) wholly aromatic and flexible diamine monomers, in which the linkage between the two aniline-ends contains a relatively high heat-tolerant but flexible chain constituted by two or more units of 1,4-phenoxy or 1,3-phenoxy or in combinations of both. Processes of making and using such all-aromatic TLC-PI is also provided.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 4, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu
  • Publication number: 20240110012
    Abstract: Crosslinkable, low-molecular-weight, main-chain thermotropic liquid-crystalline co-polyimides derived from the polycondensation of (i) liquid-crystallinity-enabling, wholly aromatic and flexible diamine monomers, in which the linkage between the two aniline-ends contains a relatively high heat-tolerant but flexible chain constituted by multiple phenoxy (MP) moieties, i.e., two or more units of 1,4-phenoxy or 1,3-phenoxy or in combinations of both. Such polyimides allow the modification of ink materials to meet varying processing conditions in additive manufacturing of devices and components that require high-temperature polymers.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 4, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu
  • Publication number: 20240114682
    Abstract: The present disclosure relates to a structure which includes a semiconductor substrate, a recessed shallow trench isolation structure within the semiconductor substrate, and a gate structure provided at least partially over the recessed shallow isolation structure.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Inventors: Xinshu CAI, Shyue Seng TAN, Eng Huat TOH
  • Publication number: 20240110011
    Abstract: Applicants disclose a family of low-molecular-weight, main-chain thermotropic liquid-crystalline polyimides (TLC-PI) that are thermally crosslinkable and processes of making and using same. Such materials provide flexibility advantage when modifying ink materials to meet varying processing conditions in additive manufacturing of devices and components that require high-temperature polymers.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 4, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu, Bingqian Zheng, Hilmar Koerner
  • Patent number: 11947868
    Abstract: A method for muting and unmuting a microphone is provided. The method includes providing a processor, receiving an input microphone signal, measuring the input microphone signal for a loudness level at a sampling rate, calculating a mute threshold level, checking if the loudness level is higher than or equal to the mute threshold level, and resetting a mute delay timer upon determining that the loudness level is higher than or equal to the mute threshold level and obtaining the input microphone signal, or checking if the mute delay timer is running upon determining that the loudness level is not higher than or equal to the mute threshold level and attenuating the input microphone signal if the mute delay timer is not running or obtaining the input microphone signal if the mute delay timer is still running, and writing the input microphone signal or attenuated input microphone signal to an output buffer.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 2, 2024
    Assignee: CREATIVE TECHNOLOGY LTD.
    Inventors: Kee Seng Tan, Luen Kai Chan, Ariel Arellano De Castro
  • Publication number: 20240101525
    Abstract: Applicants disclose a family of rod-like dianhydrides that contain two phthalic anhydride moieties linked by a bridge that is comprised of at least one ethynyl and one paraphenylene group and processes of making and using such rod-like dianhydrides. Such rod-like dianhydrides can endow net-work structures with improved mechanical and thermal properties in the crosslinked-polymer products.
    Type: Application
    Filed: April 12, 2023
    Publication date: March 28, 2024
    Inventors: Loon-Seng Tan, Zhenning Yu
  • Publication number: 20240105200
    Abstract: A method for selective noise suppression in an audio playback is provided. The method includes providing a processor, obtaining a microphone state and a playback device state with the processor from an operating system, determining the audio playback is communication audio based on the microphone state and the playback device state, and enabling applying noise suppression to the audio playback if the audio playback is communication audio, is not music and noise is present, or otherwise disabling applying noise suppression to the audio playback.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 28, 2024
    Applicant: Creative Technology Ltd
    Inventors: Kee Seng TAN, Luen Kai CHAN, Ariel Arellano DE CASTRO
  • Patent number: 11942460
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Publication number: 20240088173
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single-photon avalanche diode with isolated junctions and methods of manufacture. The structure includes a first p-n junction in a semiconductor material; and a second p-n junction in a second semiconductor material isolated from the first p-n junction by a buried insulator layer.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Xinshu CAI, Shyue Seng TAN, Eng Huat TOH, Kiok Boone Elgin QUEK
  • Patent number: 11929351
    Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Patent number: 11926726
    Abstract: The invention relates to nanohybrids that are gold nanorod J-aggregates having a broadened surface plasmonic resonance band, processes of making such gold nanorod J-aggregates and products comprising such gold nanorod J-aggregates. Such gold nanorod J-aggregates exhibit broad localized surface plasmonic reasonable range from 800 nm to 2000 nm.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 12, 2024
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Loon-Seng Tan, Zhenning Yu, Kyoungweon Park, Richard A. Vaia
  • Publication number: 20240074048
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Hong Wan Ng, Kelvin Tan Aik Boo, Seng Kim Ye, See Hiong Leow