Abstract: According to embodiments of the present invention, a photodiode detector is provided. The photodiode detector includes an optical cavity including an overlying light-receiving portion and an underlying minor; and a GeSn absorption layer. The GeSn absorption layer may be disposed within the optical cavity and arranged between the overlying light-receiving portion and the underlying mirror. The overlying light-receiving portion may be configured to receive light to be detected by the photodiode detector. According to further embodiments of the present invention, a method of fabricating a photodiode detector is also provided.

Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

Abstract: An aqueous parenteral nutrition composition includes deoxycholic acid, cytidine diphosphate-choline and choline alfoscerate. The parenteral nutrition further includes 4.5-5.5% (w/v) phosphatidylcholine, in which combination of the phosphatidycholine with cytidine diphosphate-choline and choline alfoscerate increases choline bioavailability for immediate onset of action.

Abstract: A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an n-doped source, an n-doped drain, and a doped region in a first p-well in a substrate. A floating gate may be arranged over the first p-well, whereby the doped region may be arranged at least partially under the floating gate.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer.

Abstract: According to an aspect of the present disclosure, a memory device is provided. The memory device includes a dielectric layer having a top surface, a first electrode having a bottom surface, a switching layer, and a second electrode. The bottom surface of the first electrode is arranged below the top surface of the dielectric layer. The first electrode includes a first corner having a first acute angle and a second corner having a second acute angle arranged over the top surface of the dielectric layer. The switching layer is arranged over the first electrode. The second electrode is arranged over the switching layer, and at least the first corner of the first electrode extends into the second electrode.

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

Abstract: A chair system including a main unit and an untethered chair is provided. The main unit includes a wireless transmitter, a subwoofer, an audio stream receiver and a processor. The untethered chair includes a plurality of speakers, a power source and a wireless receiver for receiving a processed audio stream from the main unit.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

Abstract: A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

Abstract: An imaging platform for capturing multiple views is provided. The imaging platform includes a desktop base, an upright element having a first end and a second end, the first end coupled to the desktop base, a first camera and a second camera positioned on at least one protruding element coupled to the upright element, the second camera facing the desktop base, a control panel for selecting a selection of a plurality of different outputs, and a processor. The processor obtains at least one camera output from the first camera and/or the second camera based on the selection of the plurality of outputs on the control panel, and provides a processed output based on the selection of the plurality of outputs on the control panel.

Abstract: Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Abstract: A non-volatile memory device and method of making the same is provided. The memory device includes a first electrode, a first hard mask on the first electrode, a second electrode on the first hard mask, a second hard mask on the second electrode, and a third electrode on the second hard mask. A switching layer is over the electrode stack and the switching layer has a first portion conformal to the side surfaces of the electrode stack.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an extrinsic base region comprising at least a plurality of gate structures on a semiconductor structure; an emitter between the plurality of gate structures; an intrinsic base region between the plurality of gate structures; and a collector region under the plurality of gate structure in the semiconductor material.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Abstract: A chair system including a main unit and an untethered chair is provided. The main unit includes a wireless transmitter, a subwoofer, an audio stream receiver and a processor. The untethered chair includes a plurality of speakers, a power source and a wireless receiver for receiving a processed audio stream from the main unit.

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.