Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an active region surrounded by an isolation structure. A floating gate may be arranged over the active region, the floating gate having a first end and a second end over the isolation structure. A first doped region may be provided in the active region adjacent to a first side of the floating gate and a second doped region may be provided in the active region adjacent to a second side of the floating gate. A first capacitor may be provided over the floating gate, whereby a first electrode of the first capacitor is electrically coupled to the floating gate. A second capacitor may be provided, whereby a first electrode of the second capacitor is over the isolation structure and adjacent to the floating gate.

Abstract: A chair system including a main unit and an untethered chair is provided. The main unit includes a wireless transmitter, a subwoofer, an audio stream receiver and a processor. The untethered chair includes a plurality of speakers, a power source and a wireless receiver for receiving a processed audio stream from the main unit.

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

Abstract: A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

Abstract: The invention generally relates to polymer nanocomposite films that possess shape memory properties at elevated temperatures. Such films can absorb microwaves, are thermally conductive, are electrically conductive and have increased mechanical strength. In addition, the present invention relates to methods of fabricating such films into 3D objects. Due to the improved properties of such films more advanced sensors and microwave shields can be constructed.

Abstract: The invention relates to bis(aniline) compounds containing multiple arylethynyl, alkylethynyl, ethynyl groups or their combinations, processes of making such compounds and materials comprising such compounds. Such, bis(aniline) compounds preferably comprise multiple phenylethynyl (PE) groups, i.e. 2-4 PE moieties. Such compounds are useful monomers for the preparation of polyimides, polyamides and poly(amide-imides) whose post-fabrication crosslinking chemistry (i.e. reaction temperature) can be controlled by the number of PE per repeat unit as well as finding utility in thermosetting matrix resins, 3D printable resins, and as high-carbon-content precursors to carbon-carbon composites.

Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween.

Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

Abstract: A memory device and method of making the same is provided. The memory device includes a first electrode, an oxygen scavenging layer on the first electrode, a hard mask on the oxygen scavenging layer, and a second electrode on the hard mask. A switching layer is arranged on a portion of the oxygen scavenging layer, and the switching layer is conformal to a side surface of the hard mask.

Abstract: Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

Abstract: The invention generally relates to shape memory films that are tri-functionally crosslinked and that comprise multiple, non-terminal, phenylethynyl moieties. In addition, the present invention relates methods of fabricating such films. Due to the improved properties of such SMPs, the SMP designer can program in to the SMP thermomechanical property enhancements that make the SMP suitable, among other things, for advanced sensors, high temperature actuators, responder matrix materials and heat responsive packaging.

Abstract: A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises an n-doped source, an n-doped drain, and a doped region in a first p-well in a substrate. A floating gate may be arranged over the first p-well, whereby the doped region may be arranged at least partially under the floating gate.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory cell and a charge-detrap electrode. The memory cell includes a substrate, a floating gate having a first side and a second side laterally opposite the first side, and a gate electrode. The substrate further includes a source region and a drain region, and a channel region arranged between the source region and the drain region. The floating gate is arranged over the channel region and the gate electrode is arranged adjacent to the first side of the floating gate. The charge-detrap electrode is arranged adjacent to the second side of the floating gate.

Abstract: A memory device may be provided. The memory device may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory device may further include a contact element arranged in the well and including a first contact having the first conductivity type; a diode layer arranged in the well and having a second conductivity type opposite to the first conductivity type; and a dummy gate configured to isolate the first contact from the diode layer. The memory device may further include a memory element electrically connected to the diode layer.

Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.