Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

Abstract: Methods of depositing a metal film are discussed. A metal film is formed on the bottom of feature having a metal bottom and dielectric sidewalls. Formation of the metal film comprises exposure to a metal precursor and an alkyl halide catalyst while the substrate is maintained at a deposition temperature. The metal precursor has a decomposition temperature above the deposition temperature. The alkyl halide comprises carbon and halogen, and the halogen comprises bromine or iodine.

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.

Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.

Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.

Abstract: Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer.

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.

Abstract: Methods for selectively depositing on non-metallic surfaces are disclosed. Some embodiments of the disclosure utilize an unsaturated hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked non-metallic surfaces. Some embodiments of the disclosure relate to methods of forming metallic vias with decreased resistance.

Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.

Abstract: Methods for forming barrier/seed layers for interconnect structures are provided. More specifically, methods of depositing a film on a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall with a dielectric surface and a bottom with a conductive surface. A manganese-ruthenium film is formed in the opening in the first surface of the substrate on the conductive surface.

Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

Abstract: Methods of depositing a metal film with high purity are discussed. Some embodiments utilize a thermal ALD process comprising an alkyl halide and a metal precursor. Some embodiments selectively deposit a metal film with high purity on a metal surface over a dielectric surface. Some embodiments selectively deposit a metal film with high purity on a dielectric surface over a metal surface. Some embodiments deposit a metal film with greater than 99% metal atoms on an atomic basis.

Abstract: Methods for depositing a film comprising exposing a substrate surface to a metal precursor and a hydrazine derivative to form a metal containing film are described.

Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.

Abstract: Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer.

Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.

Abstract: Methods for selectively depositing a metal silicide layer are provided herein.