Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.

Abstract: Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the first work function layer and the second feature.

Abstract: Methods for depositing a film comprising exposing a substrate surface to a metal precursor and a hydrazine derivative to form a metal containing film are described.

Abstract: Processing methods for depositing aluminum etch stop layers comprise positioning a substrate within a processing chamber, wherein the substrate comprises a metal surface and a dielectric surface; exposing the substrate to an aluminum precursor gas comprising an isopropoxide based aluminum precursor to selectively form an aluminum oxide (AlOx) etch stop layer onto the metal surface while leaving exposed the dielectric surface during a chemical vapor deposition process. The metal surfaces may be copper, cobalt, or tungsten.

Abstract: Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and bottom surface of the opening; and depositing a conductive material on the layer to fill the opening. In some embodiments, one of ruthenium (Ru) or cobalt (Co) is deposited on the sidewall and bottom surface of the opening. The materials may be deposited by chemical vapor deposition (CVD) or by physical vapor deposition (PVD).

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

Abstract: Films comprising Aluminum, carbon and a metal, wherein the aluminum is present in an amount greater than about 16% by elemental content and the film has less than about 50% carbon. Methods of forming the films comprise exposing a substrate to a metal halide precursor, purging the metal halide precursor from the processing chamber and then exposing the substrate to an alkyl aluminum precursor and an alane precursor, either sequentially or simultaneously. The alane precrursor comprises an amine-alane and a stabilizing amine selected from one or more of diemthylcyclohexylamine or dicyclomethylhexylamine.

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method for etching a substrate disposed within a processing volume of a process chamber includes: (a) exposing a first layer disposed atop the substrate to a first gas comprising tungsten chloride (WClx) for a first period of time and at a first pressure, wherein x is 5 or 6; (b) purging the processing volume of the first gas using an inert gas for a second period of time; (c) exposing the substrate to a hydrogen-containing gas for a third period of time to etch the first layer after purging the processing volume of the first gas; and (d) purging the processing volume of the hydrogen-containing gas using the inert gas for a fourth period of time.

Abstract: Embodiments described herein relate to a thermal chlorine gas cleaning process. In one embodiment, a method for cleaning N-Metal film deposition in a processing chamber includes positioning a dummy substrate on a substrate support. The processing chamber is heated to at least about 50 degrees Celsius. The method further includes flowing chlorine gas into the processing chamber and evacuating chlorine gas from the processing chamber. In another embodiment, a method for cleaning titanium aluminide film deposition in a processing chamber includes heating the processing chamber to a temperature between about 70 about degrees Celsius and about 100 degrees Celsius, wherein the processing chamber and the substrate support include one or more fluid channels configured to heat or cool the processing chamber and the substrate support.

Abstract: Provided are atomic layer deposition methods to deposit a film using a circular batch processing chamber with a plurality of sections separated by gas curtains so that each section independently has a process condition.

Abstract: Methods for selectively depositing a metal silicide layer are provided herein.

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method for etching a substrate disposed within a processing volume of a process chamber includes: (a) exposing a first layer disposed atop the substrate to a first gas comprising tungsten chloride (WCIx) for a first period of time and at a first pressure, wherein x is 5 or 6; (b) purging the processing volume of the first gas using an inert gas for a second period of time; (c) exposing the substrate to a hydrogen-containing gas for a third period of time to etch the first layer after purging the processing volume of the first gas; and (d) purging the processing volume of the hydrogen-containing gas using the inert gas for a fourth period of time.

Abstract: Provided are methods of depositing N-Metals onto a substrate. Methods include first depositing an initiation layer. The initiation layer may comprise or consist of cobalt, tantalum, nickel, titanium or TaAlC. These initiation layers can be used to deposit TaCx.

Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).

Abstract: Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process.

Abstract: A bridge assembly includes an electrically insulating hollow tube or bridge having a pair of ends, the bridge being supported at one of the ends over the cylindrical side wall and being supported at the other of the ends over the electrode. The bridge assembly further includes a set of conductive rings surrounding the hollow tube and spaced from one another along the length of the bridge, and plural electrically resistive elements. Each of the resistive elements has a pair of flexible connectors, respective ones the resistive elements connected at their flexible connectors between respective pairs of the rings to form a series resistor assembly.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Provided are methods of depositing films comprising alloys of aluminum, which may be suitable as N-metal films. Certain methods comprise exposing a substrate surface to a metal halide precursor comprising a metal halide selected from TiCl4, TaCl5 and HfCl4 to provide a metal halide at the substrate surface; purging metal halide; exposing the substrate surface to an alkyl aluminum precursor comprising one or more of dimethyaluminum hydride, diethylhydridoaluminum, methyldihydroaluminum, and an alkyl aluminum hydrides of the formula [(CxHy)3-aAlHa]n, wherein x has a value of 1 to 3, y has a value of 2x+2, a has a value of 1 to 2, and n has a value of 1 to 4; and exposing the substrate surface to an alane-containing precursor comprising one or more of dimethylethylamine alane, methylpyrrolidinealane, di(methylpyrolidine)alane, and trimethyl amine alane borane. Other methods comprise exposing a substrate surface to a metal precursor and trimethyl amine alane borane.