Abstract: A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.

Abstract: A storage system is provided comprising a controller and a memory comprising a plurality of tiles of memory organized in a plurality of tile groups, wherein a given tile group is busy when any tile in the given tile group is busy. The controller is configured to: inform the host of the busy status of the plurality of tile groups; receive a plurality of commands from the host, wherein each command is provided with a different tile group identifier of a tile group that is not busy; and execute the plurality of commands, wherein because each command comprises a different tile group identifier of a tile group that is not busy, the plurality of commands are executed in parallel.

Abstract: A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.

Abstract: In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, and a second sampling read operation is selectively performed to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value. The second offset read voltage is different from the first offset read voltage.

Abstract: According to one embodiment, there is provided a light control apparatus which includes: a touch screen to display a graphical user interface for controlling a light; and a wireless communication unit performing communication with a light and transmitting a control signal set through the graphical user interface to the corresponding light, wherein the graphical user interface includes a first area displaying a name of the light, and a second area displaying location information of the light selected from the first area, and the location information is spot information about an actual installed location of the light selected from the first area.

Abstract: The present disclosure, in various embodiments, describes three-dimensional (3D) vertical resistive random access memory (ReRAM) structures. In one embodiment, a memory device includes a resistive memory element and a selector coupled in series with the resistive memory element. A turn-on voltage of the selector is greater than a bias voltage of the memory device in an unselected state such that the selector remains in a turn-off state when the memory device is unselected, and the selector is configured to have substantially the same resistance in both a forward bias direction and a reverse bias direction in a turn-on state.

Abstract: Provided is a read method for a nonvolatile memory device for reading data with an optimum read voltage. The read method includes reading data of a first set of memory cells connected to a first word line, by dividing the data of the first set of memory cells into M pages and individually reading data from the M pages. The reading data includes performing an on-chip valley search (OVS) operation on a first valley of two adjacent threshold voltage distributions of the first set of memory cells when reading each of the M pages, and performing a data recover read operation via a read operation on a second word line adjacent to the first word line, based on a result of the OVS operation. In the data recover read operation, a read operation on the first word line is not performed.

Abstract: Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L?1 program states.

Abstract: In general, a controller may perform a self-virtualization technique. The storage device may include storage access comprising multiple cells, and a controller. The controller may determine a maximum amount of storage access for a virtual machine workload when each cell is configured in a first level mode having a maximum allowable number of bits per cell. The controller may configure each cell to be in a second level mode having a number of bits per cell less than the maximum. The controller may determine a total number of bits in use in each cell and compare this total to a threshold number of bits in use in each cell. Based on the comparison, the controller may reconfigure one or more cells to be in a third level mode having a number of bits per cell greater than the number for the second level mode.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.

Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Abstract: Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits.

Abstract: Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

Abstract: A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.

Abstract: According to one embodiment, there is provided a light control apparatus which includes: a touch screen to display a graphical user interface for controlling a light; and a wireless communication unit performing communication with a light and transmitting a control signal set through the graphical user interface to the corresponding light, wherein the graphical user interface includes a first area displaying a name of the light, and a second area displaying location information of the light selected from the first area, and the location information is spot information about an actual installed location of the light selected from the first area.

Abstract: Methods and systems for suppressing the latency in a non-volatile memory are provided. The non-volatile memory can include a flash memory and a storage class memory. The storage class memory can be divided in a first region and a second region. A method for suppressing the latency in the non-volatile memory can determine whether a received host command requires access to the flash memory. When the host command does not require access to the flash memory, the method can further determine whether the host command requires access to the first region or the second region of the storage class memory. The method can suppress the latency in the non-volatile memory by copying valid pages of flash memory blocks into the storage class memory.

Abstract: The present disclosure relates to apparatus, systems, and methods that address the migration of least significant in memory cells due to inter-cell interference (ICI). The disclosed embodiments include a control unit that is configured to characterize the vulnerability of memory cells to ICI, and appropriately encode data stored in the vulnerable memory cells to address ICI. This encoding scheme, referred to as “stuck-at” encoding scheme, can be separate from the generic error correcting code encoding. The stuck-at encoding scheme can decrease the bit error rate of flash memory devices.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.