Abstract: The memory device according to an embodiment may comprise a memory cell array in which memory cells of a latch structure are connected in a matrix form to word lines and bit lines and a peripheral circuit configured to supply a first voltage to the memory cells only in a developing section of a read operation for the memory cells and supply a second voltage which maintains data of the memory cells and lower than the first voltage in other sections. The peripheral circuit may be configured to supply the second voltage to the memory cells in all sections of a write operation for the memory cells.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.

Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Abstract: A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground.

Abstract: A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground.

Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.

Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.

Abstract: A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Abstract: Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.