Abstract: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Abstract: Clock pads are distributed over an integrated circuit memory device and electrically connected to a lead frame to synchronously provide an external clock signal to the clock pads. Accordingly, an internal clock signal is generated throughout the integrated circuit memory device by distributing an external clock signal using a lead frame and pads. Internal circuitry for generating and synchronizing an internal clock from an external clock is thereby not required. When the integrated circuit memory device includes multiple memory array banks, the clock pads may be located in a row of input/output pads adjacent a memory array bank or between pairs of memory array banks.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Abstract: A memory module having parity and capable of performing a read-modify-write (RMW) operation is provided. The memory module has data input and output pins for processing a plurality of data bits and a parity bit and is comprised of one semiconductor memory device which processes the parity bit and a plurality of semiconductor memory devices which each process a plurality of data bits. All of the memory devices include at least one data input/output pin for receiving and supplying data and at least one control pin for receiving a control signal. The memory module according to the present invention is simply constructed so as to yield high integration in a semiconductor integrated circuit, and is capable of high-speed applications.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract: A half power supply voltage generating circuit receiving first and second power supply voltages and comprising; a bias circuit for generating first and second reference voltages in response to the first and second power supply voltages, and a driver circuit receiving the first and second reference voltages and generating a half power supply voltage, the driver circuit comprising four MOS transistors connected in series between the first and second supply voltages.

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.