Patents by Inventor Seung-Moon Yoo
Seung-Moon Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6825694Abstract: A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.Type: GrantFiled: September 26, 2002Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventor: Seung-Moon Yoo
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Patent number: 6812739Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: GrantFiled: September 26, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
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Publication number: 20040157569Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Inventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
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Patent number: 6759873Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.Type: GrantFiled: May 21, 2002Date of Patent: July 6, 2004Assignee: The Board of Trustees of the University of IllinoisInventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20040113672Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.Type: ApplicationFiled: December 5, 2003Publication date: June 17, 2004Inventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20040079978Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate cType: ApplicationFiled: March 27, 2003Publication date: April 29, 2004Inventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20040061523Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: International Business Machine CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
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Publication number: 20040061531Abstract: A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: International Business Machines CorporationInventor: Seung-Moon Yoo
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Publication number: 20040041594Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.Type: ApplicationFiled: December 20, 2002Publication date: March 4, 2004Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20040017711Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and tType: ApplicationFiled: March 27, 2003Publication date: January 29, 2004Inventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20030030484Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.Type: ApplicationFiled: May 22, 2002Publication date: February 13, 2003Inventors: Sung-Mo Kang, Seung-Moon Yoo
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Publication number: 20020175710Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.Type: ApplicationFiled: May 21, 2002Publication date: November 28, 2002Applicant: The Board of Trustees of the University of IllinoisInventors: Seung-Moon Yoo, Sung-Mo Kang
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Patent number: 5892386Abstract: An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.Type: GrantFiled: December 5, 1996Date of Patent: April 6, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-chan Lee, Jung-hwa Lee, Seung-moon Yoo
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Patent number: 5889719Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.Type: GrantFiled: August 7, 1995Date of Patent: March 30, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Moon Yoo, Ejaz ul Haq, Yun-Ho Choi, Soo-In Cho, Dae-Je Chin, Nam-Soo Kang, Seung-Hun Lee
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Patent number: 5845108Abstract: A semiconductor memory device such as a DRAM has an internal oscillator to provide a periodic clock signal. During a read operation, output data is generated synchronized to the internal clock signal, and an external control signal is provided also synchronized to the internal clock signal. A requesting device utilizes the external control signal for fetching data from the memory device at high speed with improved setup and hold time. The control signal output is active only during a read operation, thereby reducing power consumption. Additionally, a common line is used for receiving address, instructions, and data. This drastically reduces the number of pins for interfacing to a memory device.Type: GrantFiled: December 19, 1996Date of Patent: December 1, 1998Assignee: Samsung Electronics, Co., Ltd.Inventors: Seung-Moon Yoo, Ejaz Ul Haq
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Patent number: 5808955Abstract: An integrated circuit memory device includes a main row decoder, a sub-row decoder, and a sub-word line driver. The main row decoder decodes the first portion of a row address, and generates a main row activation signal when one of the plurality of rows have been selected. The sub-row decoder decodes a second portion of the row address, and generates a first sub-row activation signal when a first one of the plurality of rows has been selected. The sub-row decoder generates a second sub-row activation signal when a second one of the plurality of rows has been selected. The sub-word line driver activates a first memory cell in the first row in response to the main row activation signal and the first sub-row activation signal. The sub-word line driver activates a second memory cell of the second row in response to the main row activation signal and the second sub-row activation signal.Type: GrantFiled: July 15, 1996Date of Patent: September 15, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sun Hwang, Seung-Moon Yoo
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Patent number: 5771198Abstract: An internal power supply circuit for a semiconductor memory device comprising a differential amplifier having a reference voltage as an input and utilizing an external power supply voltage. An amplifier output provides an internal power supply voltage. The amplifier is connected to a current source which comprises a plurality of transistors connected in series between one side of said amplifier and ground. A current control transistor having a channel larger than the channels of the transistors connected in series is switchable between a first state in which the current control transistor is substantially on and a second state in which said current control transistor is substantially off.Type: GrantFiled: April 22, 1996Date of Patent: June 23, 1998Assignee: Samsung Electronics Co. Ltd.Inventors: Bok-Moon Kang, Seung-Moon Yoo
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Patent number: 5744997Abstract: A substrate bias voltage controlling circuit controls the generation of different substrate bias voltages according to specific modes. A first sensing signal generator is controlled by the substrate bias voltage and generates a first sensing signal when the level of the substrate bias voltage is higher than a predetermined first potential level. A second sensing signal generator is controlled by the substrate bias voltage and a specific mode signal and generates a second sensing signal when the level of the substrate bias voltage is higher than a predetermined second potential level and when the mode signal is enabled.Type: GrantFiled: April 26, 1996Date of Patent: April 28, 1998Assignee: Samsung Electronics, Co., Ltd.Inventors: Bok-Moon Kang, Seung-Moon Yoo
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Patent number: 5703811Abstract: A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors.Type: GrantFiled: December 29, 1995Date of Patent: December 30, 1997Assignee: Samsung Electronocs Co., Ltd.Inventors: Seung-Moon Yoo, Jei-Hwon Yoo
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Patent number: 5668497Abstract: Disclosed is a DC voltage generating circuit for reducing an electric power consumption in a semiconductor memory device. The DC voltage generating circuit comprises: a refresh counter for setting a refresh cycle; a power source supply controller for logically combining a counting value supplied from the refresh counter and a self-refresh timer driving signal, thereby to generate a power source supply control signal in a refresh section; and a DC voltage generator for generating and supplying a DC voltage through an output terminal of the DC voltage generator, as controlled by the power source supply control signal supplied from the power source supply controller.Type: GrantFiled: December 18, 1995Date of Patent: September 16, 1997Assignee: Samsung Electronics Co., Ltd.Inventors: Bok-Moon Kang, Seung-Moon Yoo