Patents by Inventor Seung-nam Cha

Seung-nam Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7719111
    Abstract: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 18, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Yong-Wan Jin, Byong-Gwon Song
  • Publication number: 20100060825
    Abstract: A display apparatus includes an active transflective device and a device panel. The active transflective device is configured to electrically control light transmissivity and light reflectivity. The display panel is configured to form an image by modulating at least one of light reflected and light transmitted by the active transflective device.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Inventors: Jae-eun Jang, Seung-nam Cha, Jae-eun Jung, Yong-wan Jin
  • Publication number: 20090258188
    Abstract: Disclosed herein is a composition for forming an inorganic pattern, comprising an inorganic precursor, at least one stabilizer selected from ?-diketone and ?-ketoester, and a solvent. Use of the composition enables efficient and inexpensive formation of an inorganic micropattern.
    Type: Application
    Filed: August 28, 2008
    Publication date: October 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Dae Joon KANG, Byong Gwon SONG
  • Publication number: 20090235862
    Abstract: A method of manufacturing zinc oxide nanowires. A metal seed layer is formed on a substrate. The metal seed layer is thermally oxidized to form metal oxide crystals. Zinc oxide nanowires are grown on the metal oxide crystals serving as seeds for growth. The zinc oxide nanowires are aligned in one direction with respect to the surface of the substrate.
    Type: Application
    Filed: September 24, 2008
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Jae Eun JANG, Byong Gwon SONG
  • Publication number: 20090206321
    Abstract: A thin film transistor includes nanowires. More specifically, the thin film transistor includes nanowires aligned between and extending to opposite facing lateral surfaces of source/drain electrodes on a substrate. The nanowires extend in a direction parallel to a major surface defining the substrate to form a semiconductor channel layer. Also disclosed herein is a method for fabricating the thin film transistor.
    Type: Application
    Filed: October 1, 2008
    Publication date: August 20, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Byong Gwon SONG, Jae Eun JANG
  • Patent number: 7564085
    Abstract: A memory device that performs writing and reading operations using a mechanical movement of a nanowire, and a method of manufacturing the memory device are provided. The memory device includes a source electrode, a drain electrode, and a gate electrode, each of which is formed on an insulating substrate. A nanowire capacitor is formed on the source electrode. The nanowire capacitor includes a first nanowire vertically grown from the source electrode, a dielectric layer formed on the outer surface of the first nanowire, and a floating electrode formed on the outer surface of the dielectric layer. A second nanowire is vertically grown on the drain electrode. The drain electrode is arranged between the source electrode and the gate electrode. The second nanowire is elastically deformed and contacts the nanowire capacitor when a drain voltage is applied to the drain electrode, and polarity of the drain voltage is opposite to polarity of a source voltage that is applied to the source electrode.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: July 21, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Byong-Gwon Song, Yong-Wan Jin
  • Publication number: 20090161195
    Abstract: A color pixel structure of a color display system based on electrochromism. The color pixel structure includes two one-cell two-color type unit cells laminated. Each of the unit cells includes an upper panel, a lower panel and electrochromic materials of different colors applied to both the upper and lower panels. The color pixel structure exhibits improved color characteristics and have a simple structure. The color pixel structure can be applied to a variety of electrochromic displays due to their excellent visibility and simple structure.
    Type: Application
    Filed: June 11, 2008
    Publication date: June 25, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Eun Jang, Seung Nam Cha, Jae Eun Jung, Chang Ho Noh
  • Publication number: 20090121219
    Abstract: Provided is a method of growing carbon nanotubes (CNTs) by forming a catalyst layer that is used to facilitate growth of CNTs to have a multi-layer structure; and injecting a carbon-containing gas to the catalyst layer to grow CNTs, and light emitting devices fabricated by incorporating the CNTs grown.
    Type: Application
    Filed: September 12, 2008
    Publication date: May 14, 2009
    Inventors: Byong-gwon Song, Jin-pyo Hong, Yong-wan Jin, Seung-nam Cha, Jong-hyun Lee, Jae-hwan Ha
  • Patent number: 7532383
    Abstract: An electrochromic device which includes a display electrode including a conductive layer disposed on a transparent substrate, a counter electrode disposed to face the display electrode, the counter electrode including a white reflective layer, an electrolyte interposed between the display electrode and the counter electrode, a first electrochromic material layer disposed on the display electrode and a second electrochromic material layer disposed on the counter electrode.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Eun Jang, Jae Eun Jung, Seung Nam Cha, Chang Ho Noh
  • Publication number: 20090098043
    Abstract: Example embodiments provide a method for preparing zinc oxide nanostructures. According to the method, zinc oxide nanostructures are prepared by dipping a substrate having a zinc (Zn) seed layer thereon in an aqueous solution of hexamethyleneamine and dropwise adding an aqueous solution of zinc nitrate to the aqueous solution of hexamethyleneamine. In addition, zinc ions can be continuously supplied in a constant amount as the reactions of the reactants proceed to prepare high-quality zinc oxide nanostructures at a high growth rate. Furthermore, zinc oxide nanostructures can be prepared on a large-area substrate at a low processing temperature regardless of the substrate material. Example embodiments also provide zinc oxide nanostructures prepared by the method.
    Type: Application
    Filed: March 24, 2008
    Publication date: April 16, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byong Gwon SONG, Seung Nam CHA, Jae Eun JUNG, Jae Eun JANG
  • Publication number: 20080278792
    Abstract: An electrochromic device which includes a display electrode including a conductive layer disposed on a transparent substrate, a counter electrode disposed to face the display electrode, the counter electrode including a white reflective layer, an electrolyte interposed between the display electrode and the counter electrode, a first electrochromic material layer disposed on the display electrode and a second electrochromic material layer disposed on the counter electrode.
    Type: Application
    Filed: October 24, 2007
    Publication date: November 13, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Eun JANG, Jae Eun JUNG, Seung Nam CHA, Chang Ho NOH
  • Publication number: 20080230853
    Abstract: In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer surrounding the channel layer between the source electrode and the drain electrode, and a gate electrode surrounding the gate insulating layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: September 25, 2008
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Jae-Eun Jung, Yong-Wan Jin
  • Publication number: 20080164805
    Abstract: Provided is an anode panel of a field emission type backlight unit. The anode panel includes a substrate, an anode formed on a lower surface of the substrate, a phosphor layer coated on a lower surface of the anode and a liquid pack disposed on an upper surface of the substrate, said liquid pack having a transparent cover having cylindrical lens type curved portions and transparent liquid filling in the curved portions.
    Type: Application
    Filed: November 29, 2007
    Publication date: July 10, 2008
    Inventors: Byong-gwon Song, Seung-nam Cha, Sun-il Kim, Ho-suk Kang, Yong-wan Jin, Min-jong Bae
  • Publication number: 20080150043
    Abstract: A transistor includes: a semiconductor substrate; a channel region arranged on the semiconductor substrate; a source and a drain respectively arranged on either side of the channel region; and a conductive nano tube gate arranged on the semiconductor substrate to transverse the channel region between the source and the drain. Its method of manufacture includes: arranging a conductive nano tube on a surface of a semiconductor substrate; defining source and drain regions having predetermined sizes and traversing the nano tube; forming a metal layer on the source and drain regions; removing a portion of the metal layer formed on the nano tube to respectively form source and drain electrodes separated from the metal layer on either side of the nano tube; and doping a channel region below the nano tube arranged between the source and drain electrodes by ion-implanting.
    Type: Application
    Filed: July 12, 2007
    Publication date: June 26, 2008
    Inventors: Seung-Nam Cha, Jae-Eun Jang, Jae-Eun Jung, Yong-Wan Jin, Byong-Gwon Song
  • Publication number: 20080061351
    Abstract: A nanowire electromechanical switching device is constructed with a source electrode and a drain electrode disposed on an insulating substrate and spaced apart from each other, a first nanowire vertically grown on the source electrode and to which a V1 voltage is applied, a second nanowire vertically grown on the drain electrode and to which a V2 voltage having an opposite polarity to that of the V1 voltage is applied, and a gate electrode spaced apart from the second nanowire, partially surrounding the second nanowire and having an opening that faces the first nanowire in order to avoid disturbing a mutual switching operation of the first nanowire and the second nanowire and to which a V3 voltage having the same polarity as that of the V2 voltage is applied.
    Type: Application
    Filed: August 14, 2007
    Publication date: March 13, 2008
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Byong-Gwon Song, Yong-Wan Jin
  • Publication number: 20070138525
    Abstract: A memory device that performs writing and reading operations using a mechanical movement of a nanowire, and a method of manufacturing the memory device are provided. The memory device includes a source electrode, a drain electrode, and a gate electrode, each of which is formed on an insulating substrate. A nanowire capacitor is formed on the source electrode. The nanowire capacitor includes a first nanowire vertically grown from the source electrode, a dielectric layer formed on the outer surface of the first nanowire, and a floating electrode formed on the outer surface of the dielectric layer. A second nanowire is vertically grown on the drain electrode. The drain electrode is arranged between the source electrode and the gate electrode. The second nanowire is elastically deformed and contacts the nanowire capacitor when a drain voltage is applied to the drain electrode, and polarity of the drain voltage is opposite to polarity of a source voltage that is applied to the source electrode.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 21, 2007
    Inventors: Jae-Eun Jang, Seung-Nam Cha, Byong-Gwon Song, Yong-Wan Jin
  • Publication number: 20070051970
    Abstract: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics.
    Type: Application
    Filed: April 21, 2006
    Publication date: March 8, 2007
    Inventors: Jae-Eun Jang, Seung-nam Cha, Yong-Wan Jin, Byong-Gwon Song
  • Patent number: 6927534
    Abstract: A field emission device (FED) and a method for fabricating the FED are provided. The FED includes micro-tips with nano-sized surface features, and a focus gate electrode over a gate electrode, wherein one or more gates of the gate electrode is exposed through a single opening of the focus gate electrode. In the FED, occurrence of arcing is suppressed. Although an arcing occurs in the FED, damage of a cathode and a resistor layer is prevented, so that a higher working voltage can be applied to the anode. Also, due to the micro-tips with nano-sized surface features, the emission current density of the FED increases, so that a high-brightness display can be achieved with the FED. The gate turn-on voltage can be lowered due to the micro-tip as a collection of nano-sized tips, thereby reducing power consumption.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: August 9, 2005
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jun-hee Choi, Seung-nam Cha, Hang-woo Lee
  • Patent number: 6809464
    Abstract: A field emission device (FED) and a method for fabricating the FED are provided. The FED includes micro-tips with nano-sized surface features. Due to the micro-tips as a collection of a large number of nano-tips, the FED is operable at low gate turn-on voltages with high emission current densities, thereby lowering power consumption.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: October 26, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jun-hee Choi, Seung-nam Cha, Hang-woo Lee
  • Patent number: 6749477
    Abstract: A forming method of spacers in a flat panel display is provided. The method includes the steps of preparing a plurality of spacers in a predetermined shape, preparing a substrate on which the spacers are to be attached in the flat panel display, applying a photosensitive adhesive material on an upper surface of the substrate to a predetermined thickness, aligning the spacers on the substrate to attach the spacers by using the photosensitive adhesive material, radiating light onto the substrate from above the substrate to expose portions of the photosensitive adhesive material without the spacers, and removing the exposed portions of the photosensitive adhesive material. Therefore, the spacers are fixed on the substrate by the photosensitive adhesive material located under the spacers. According to the provided method of forming spacers, the spacers are fixed on the substrate by a mounting process using a jig, a temporary exposing process, and a developing process.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 15, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Kyung-won Min, Seung-nam Cha