Patents by Inventor Shafaat Ahmed
Shafaat Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105588Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Ilya V. Karpov, Shafaat Ahmed, Matthew V. Metz, Darren Anthony Denardis, Nafees Aminul Kabir, Tristan A. Tronic
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Publication number: 20230422639Abstract: A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Shafaat Ahmed, Gowtham Sriram Jawaharram, Cyrus M. Fox, Jose L. Cruz-Campa, Kriti Agarwal, Jian Jiao, Hong Li, Bharat V. Krishnan, Ervin T. Hill, III
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Publication number: 20230354723Abstract: In one embodiment, a crosspoint memory device is manufactured by forming a material stack and patterning the material stack to form a plurality of memory cells of the cross point memory device. Forming the material stack includes depositing a select device (SD) region material comprising chalcogenide, depositing a layer comprising carbon on the SD region material at a temperature below 40° C., depositing an ohmic contact layer on the layer comprising carbon, and depositing a phase change material (PM) region material comprising chalcogenide on the ohmic contact layer.Type: ApplicationFiled: May 2, 2022Publication date: November 2, 2023Applicant: Intel CorporationInventors: Gowtham Sriram Jawaharram, Cyrus M. Fox, Jose L. Cruz-Campa, Shafaat Ahmed, Qiaoer Zhou, Duo Li, Hong Li
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Publication number: 20230276639Abstract: A memory device comprising a memory array comprising a plurality of memory cells and a metal silicide layer, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupling a storage element to the first access line, wherein the metal silicide layer is between the electrode and the first access line.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Applicant: Intel CorporationInventors: Viswas Reddy Pola, Shafaat Ahmed, Gowtham Sriram Jawaharram, Gregory C. Herdt
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Publication number: 20230209834Abstract: A memory device comprising a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupled to a storage element, wherein the electrode comprises silicon carbide (SixCy).Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Shafaat Ahmed, Cyrus M. Fox, Gregory C. Herdt, Gowtham Sriram Jawaharram, Viswas Reddy Pola
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Publication number: 20230207459Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to patterning and metallization to produce metal features on a substrate that have pitches less than 26 nm. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Shafaat AHMED, Greg HERDT
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Publication number: 20230157035Abstract: An apparatus comprising a substrate; and an interconnect comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Applicant: Intel CorporationInventors: Shafaat Ahmed, Viswas Reddy Pola, Gregory C. Herdt
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Patent number: 10811547Abstract: A chalcogen-resistant material including at least one of a conductive elongated nanostructure layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide material layer is deposited over the chalcogen-resistant material. The conductive elongated nanostructures, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by blocking chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.Type: GrantFiled: September 12, 2016Date of Patent: October 20, 2020Assignee: International Business Machines CorporationInventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw
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Patent number: 10655237Abstract: Techniques for electrodepositing selenium (Se)-containing films are provided. In one aspect, a method of preparing a Se electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of selenium oxide; an acid selected from the group consisting of alkane sulfonic acid, alkene sulfonic acid, aryl sulfonic acid, heterocyclic sulfonic acid, aromatic sulfonic acid and perchloric acid; and a solvent. A pH of the solution is then adjusted to from about 2.0 to about 3.0. The pH of the solution can be adjusted to from about 2.0 to about 3.0 by adding a base (e.g., sodium hydroxide) to the solution. A Se electroplating solution, an electroplating method and a method for fabricating a photovoltaic device are also provided.Type: GrantFiled: October 29, 2017Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Shafaat Ahmed, Hariklia Deligianni
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Publication number: 20190206729Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.Type: ApplicationFiled: January 2, 2018Publication date: July 4, 2019Inventors: Qiang FANG, Shafaat AHMED, Zhiguo SUN, Jiehui SHU, Dinesh R. KOLI, Wei-Tsu TSENG
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Patent number: 10340183Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.Type: GrantFiled: January 2, 2018Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Qiang Fang, Shafaat Ahmed, Zhiguo Sun, Jiehui Shu, Dinesh R. Koli, Wei-Tsu Tseng
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Patent number: 10262942Abstract: The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.Type: GrantFiled: July 27, 2017Date of Patent: April 16, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Qiang Fang, Haigou Huang, Shafaat Ahmed, Changhong Wu, Dinesh R. Koli
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Publication number: 20190035739Abstract: The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.Type: ApplicationFiled: July 27, 2017Publication date: January 31, 2019Inventors: Qiang Fang, Haigou Huang, Shafaat Ahmed, Changhong Wu, Dinesh R. Koli
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Publication number: 20190019862Abstract: Methods for preventing fin bending in FinFET devices and related devices are provided. Embodiments include forming fins in a substrate; forming a non-conformal sacrificial layer over and between the fins to structurally conjoin the fins or an array of fins for structural integrity; forming a first gap-fill dielectric over the sacrificial layer and fins; recessing the first gap-fill dielectric to expose an upper portion of the fins and sacrificial layer; etching the sacrificial layer to expose the fins; forming a second gap-fill dielectric over the first gap-fill dielectric and over and between the fins; and recessing the second gap-fill dielectric to expose the upper portion of the fins.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventors: A K M Zahidur Rahim CHOWDHURY, Shahrukh Akbar KHAN, Joseph SHEPARD, JR., Mohammad HASANUZZAMAN, Naved A. SIDDIQUI, Shafaat AHMED
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Patent number: 10109521Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.Type: GrantFiled: May 26, 2017Date of Patent: October 23, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Qiang Fang, Shafaat Ahmed, Changhong Wu, Zhiguo Sun, Jiehui Shu
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Patent number: 10020260Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.Type: GrantFiled: December 22, 2016Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shafaat Ahmed, Benjamin G. Moser, Vimal Kumar Kamineni, Dinesh Koli, Vishal Chhabra
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Publication number: 20180182708Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Shafaat AHMED, Benjamin G. MOSER, Vimal Kumar KAMINENI, Dinesh KOLI, Vishal CHHABRA
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Patent number: 9899324Abstract: A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.Type: GrantFiled: November 28, 2016Date of Patent: February 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shafaat Ahmed, Sadanand Vinayak Despande, Atsushi Ogino
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Publication number: 20180044811Abstract: Techniques for electrodepositing selenium (Se)-containing films are provided. In one aspect, a method of preparing a Se electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of selenium oxide; an acid selected from the group consisting of alkane sulfonic acid, alkene sulfonic acid, aryl sulfonic acid, heterocyclic sulfonic acid, aromatic sulfonic acid and perchloric acid; and a solvent. A pH of the solution is then adjusted to from about 2.0 to about 3.0. The pH of the solution can be adjusted to from about 2.0 to about 3.0 by adding a base (e.g., sodium hydroxide) to the solution. A Se electroplating solution, an electroplating method and a method for fabricating a photovoltaic device are also provided.Type: ApplicationFiled: October 29, 2017Publication date: February 15, 2018Inventors: Shafaat Ahmed, Hariklia Deligianni
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Publication number: 20180019162Abstract: A method of forming an amorphous carbon (aC) layer as a barrier layer for preventing etching of metals in a dual damascene metallization process and the resulting device are provided. Embodiments include forming an inter-layer dielectric (ILD) layer over a substrate with the first ILD having recesses for a first metallization layer. Then forming a TaN barrier layer and Co liner in the recesses, filling the recesses with a metal, forming a Co cap layer over the metal and forming a conformal aC layer over the substrate are accomplished. Furthermore, an Nblock layer, an ILD layer and a metal hard mask layer completes the stack on top to the aC layer. Subsequently, the embodiments include etching vias through this stack down to the aC layer, thereby protecting the first metallized layer.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Shafaat AHMED, Shahrukh Akbar KHAN, Vishal CHHABRA