Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.

Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Abstract: A method of forming an optical bench includes forming a reflector layer over a sloping side of a substrate. The method includes depositing a redistribution layer over the substrate. The method includes disposing an under bump metallization (UBM) layer over the redistribution layer. The method includes forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer. The method includes mounting a first optical component over an uppermost portion of the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the first optical component, and the first optical component is mounted outside the trench.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A semiconductor device and a method of forming the device are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A package includes a first die, a second die, a semiconductor frame, and a reinforcement structure. The first die has a first surface and a second surface opposite to the first surface. The first die includes grooves on the first surface. The second die and the semiconductor frame are disposed side by side over the first surface of the first die. The semiconductor frame has at least one notch exposing the grooves of the first die. The reinforcement structure is disposed on the second surface of the first die. The reinforcement structure includes a first portion aligned with the grooves.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

Abstract: A package includes a first die, a second die, a semiconductor frame, and a reinforcement structure. The first di has a first surface and a second surface opposite to the first surface. The first die includes grooves on the first surface. The second die and the semiconductor frame are disposed side by side over the first surface of the first die. The semiconductor frame has at least one notch exposing the grooves of the first die. The reinforcement structure is disposed on the second surface of the first die. The reinforcement structure includes a first portion aligned with the grooves.

Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.