Abstract: In some aspects, the present disclosure provides a method for communicating audio data. In one example, the method includes determining whether a condition for each transport opportunity on an audio channel is met based on an audio sample rate and a channel rate of the audio channel. For each transport opportunity, upon determining that the condition is met for the transport opportunity, the method also includes transmitting audio sample data over the transport opportunity or receiving audio sample data at the transport opportunity.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a user equipment (UE) may receive a first signal associated with a first radio access technology (RAT) and receive a second signal associated with a second RAT. In some aspects, the UE may include one or more receiver chains associated with the first RAT and at least one receiver chain associated with the second RAT. The UE may couple, via one or more switches and based at least in part on respective energy levels associated with the first signal and the second signal satisfying one or more conditions, an output from a front end of the at least one receiver chain associated with the second RAT to the one or more receiver chains associated with the first RAT. Numerous other aspects are provided.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

Abstract: Systems and methods for power conservation on an audio bus through clock manipulation allow a clock signal on an audio bus such as a SOUNDWIRE audio bus to be stopped when there are no pending commands from a master device. The clock signal may resume when a new command from the master device is generated or the master device receives an interrupt from a slave device.

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

Abstract: Systems, methods, and apparatus associated with a device coupled to a serial bus are described. A method data communication includes providing a clock signal on a first line of the serial bus, determining a winning device based on an address received from a second line of the serial bus during a bus arbitration procedure, determining a first sampling point for sampling a first data signal that is received from the second line of the serial bus based on timing of the clock signal and a first delay value corresponding to the winning device, and capturing a first bit of data from the second line of the serial bus at the sampling point. The serial bus may be operated in accordance with an I3C protocol.

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A method for managing transactions executed on a serial bus includes configuring a slave device with information identifying a first timeslot in a first transaction type that is conducted repetitively in accordance with a repetitive time period (RTP) schedule, initiating a first transaction of the first transaction type at a first point in time that is defined by the RTP schedule, and exchanging first data with the slave device during the first timeslot in the first transaction. The serial bus may be operated in accordance with an asynchronous protocol. In one example, the asynchronous protocol is an I3C protocol.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

Abstract: Systems and methods for payload transport for simple pulse division multiplexed (PDM) devices provide for simple PDM devices to have a phase-locked loop (PLL) that operates at a frequency corresponding to an audio rate on an associated audio bus. Additional parameters are defined relative to a starting synchronization event. The parameters inform a simple PDM device from which bit slots to extract data or into which bit slots to write data. In a further exemplary aspect, a low-cost delay-locked loop (DLL) is used to assist the simple PDM device in calculating the designated bit slots.

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

Abstract: Methods and apparatuses for aggregated IBIs are provided. The apparatus includes a host controller configured to communicate with at least one slave via a serial communication bus, trigger and receive a series of responses from the at least one slave via the serial communication bus, determine one response of the series of responses indicating an in-band interrupt (IBI) request, and respond to the IBI request based on a position of the one response among the series of responses. The method includes communicating with at least one slave via a serial communication bus, triggering and receiving a series of responses from the at least one slave via the serial communication bus, determining one response of the series of responses indicating an in-band interrupt (IBI) request, and responding to the IBI request based on a position of the one response among the series of responses.

Abstract: Methods and apparatuses for IBI handling are provided. The apparatus includes at least one processing unit, a host controller configured to communicate with at least one slave via an I3C link and configured to enter into a low-power mode. The I3C link includes a serial clock (SCL) line and a serial data (SDA) line. The apparatus further includes an IBI detection module configured to detect while the host controller is in the low-power mode, on the SDA line, an in-band interrupt (IBI) request from the at least one slave and a processing unit interrupt control module configured to signal a processing unit interrupt to the at least one processing unit based on information of the IBI request, in the case the host controller is in the low-power mode, in response to the IBI detection module detecting the IBI request.