Abstract: Systems, methods, and apparatus are described that enable communication of signals over a serial data bus. A method performed at a transmitter/sender device coupled to the serial data bus includes determining at a transmitter on the serial data bus a condition whereby a receiver in communication with the transmitter on the serial data bus is initiating a termination of data transfer between the transmitter and the receiver. The method further includes calculating an error check word in the transmitter simultaneous with data transfer from the transmitter to the receiver, and temporarily taking control of the serial bus with the transmitter after initiation of the termination of data transfer and transmitting the calculated error check word to the receiver.

Abstract: A serial low-power inter-chip media bus (SLIMbus) communications link is deployed in apparatus having multiple integrated circuit (IC) devices. Systems, methods and apparatus are described that can improve the operation of SLIMbus communications links. A method includes determining that an interrupt asserted within a first device coupled to a SLIMbus is directed to a second device coupled to the SLIMbus and generating an in-band interrupt (IBI) message identifying the first device as an interrupt source, the second device as an interrupt target, and including information identifying a type and a status associated with the interrupt, and transmitting the IBI message to the second device over the SLIMbus.

Abstract: Selective processor wake-up in an electronic device is provided. In one aspect, a master circuit in an electronic device is communicatively coupled to a data bus that includes a primary data line and a plurality of secondary data lines preconfigured to identify a plurality of processors in the electronic device, respectively. The master circuit detects a processor wake-up trigger(s) asserted on a secondary data line(s) and wakes up a target processor(s) identified by the secondary data line(s). In another aspect, a client circuit(s) identifies the secondary data line(s) preconfigured to identify the target processor(s) and asserts the processor wake-up trigger(s) on the secondary data line(s). By conveying the processor wake-up trigger(s) over the secondary data line(s) preconfigured to identify the target processor(s), it may be possible to optimize processor wake-up efficiency and responsiveness in the master circuit, thus leading to improved power consumption and battery life in the electronic device.

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract: An embodiment of the invention provides a communication device (500, 800) which comprises a communication entity (502, 802) and a further communication entity (504, 804) communicatively coupled to the communication entity (502, 802) in accordance with a Digital Radio Frequency protocol. The communication entity (502, 802) comprises a protocol layer (516), the further communication entity (504, 804) comprises a protocol layer (514), and the protocol layers (516, 514) of the communication entity (502, 802) and of the further communication entity (504, 804) are connected via a protocol-physical interface (512, 513) which provides for a parallel bidirectional signal interfacing. The protocol-physical interface (512, 513) is adapted for selectively connecting the protocol layers (516, 514) directly or via physical layers (503, 508).

Abstract: An embodiment of the invention provides a communication device (500, 800) which comprises a communication entity (502, 802) and a further communication entity (504, 804) communicatively coupled to the communication entity (502, 802) in accordance with a Digital Radio Frequency protocol. The communication entity (502, 802) comprises a protocol layer (516), the further communication entity (504, 804) comprises a protocol layer (514), and the protocol layers (516, 514) of the communication entity (502, 802) and of the further communication entity (504, 804) are connected via a protocol-physical interface (512, 513) which provides for a parallel bidirectional signal interfacing. The protocol-physical interface (512, 513) is adapted for selectively connecting the protocol layers (516, 514) directly or via physical layers (503, 508).