Abstract: Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.

Abstract: Exemplary aspects of the present disclosure assist in phase alignment for systems having multiple audio sources. For example, in a system having plural microphones, phase alignment may also be assisted by sampling the microphones at the appropriate time relative to when the samples are placed on the audio bus. Further, phase shifts between audio samples are reduced or eliminated by keeping a sample delay constant for samples from the same microphone. Such manipulation of the audio samples reduces phase shifts which reduces the likelihood of an audio artifact capable of being detected by the human ear and thus improves consumer experience.

Abstract: Delayed bank switch commands in an audio system such as a SOUNDWIRE audio system may have slaves that have had a delay register added to register banks for each data port. When a bank switch command is received, a slave consults the delay register and delays switching by a number of frames indicated in the delay register. Such delays may be used to prevent interpreting non-audio data as part of a data stream, particularly at start up and closure of audio streams. If an audio stream is active, the delay may be set to zero. By precluding the evaluation of non-audio data, audio artifacts may be avoided and a better user experience provided.

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

Abstract: Systems, methods, and apparatus are described for communicating virtual GPIO (VGI) information between multiple source devices and multiple consuming devices. A method for facilitating communication of VGI state over a serial bus includes determining that an in-band interrupt has been asserted on the serial bus while the serial bus is idle, participating in an exchange of VGI state when a first bit of a device address transmitted during bus arbitration associated with the in-band interrupt has a first value, receiving a plurality of bits of VGI state during the exchange of VGI state, including bits transmitted by multiple devices coupled to the serial bus, and mapping at least one bit in the plurality of bits of VGI state to a physical GPIO pin. Transmission of at least a second bit of the device address is suppressed when the first bit of a device address has the first value.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

Abstract: Lightweight Universal Serial Bus (USB) compound device implementation is disclosed. In particular, a compound device is provided that includes a parsing circuit that parses addresses and endpoint values for comparison to a look-up table and translation thereof for provision of updated addresses and endpoint values to a USB device controller. The USB device controller then uses the updated endpoint values to route information to a correct destination. In this manner, the benefits of a USB compound device are provided without the area and power penalty that normally accompanies a USB compound device.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a data frame to be transmitted over a plurality of data lanes of a multilane serial bus, providing a preamble to precede the data payload in transmission over the multilane serial bus, configuring one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame, and transmitting the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus. At least one bit of the multi-bit cyclic redundancy check is transmitted on two or more data lanes of the plurality of data lanes.

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Abstract: Exemplary aspects of the present disclosure assist in phase alignment for systems having multiple audio sources. For example, in a system having plural microphones, phase alignment may also be assisted by sampling the microphones at the appropriate time relative to when the samples are placed on the audio bus. Further, phase shifts between audio samples are reduced or eliminated by keeping a sample delay constant for samples from the same microphone. Such manipulation of the audio samples reduces phase shifts which reduces the likelihood of an audio artifact capable of being detected by the human ear and thus improves consumer experience.

Abstract: Event-based branching for serial protocol processor-based devices is disclosed. In this regard, a serial protocol processor-based device provides an event mesh control circuit comprising a mapping table circuit and a register control array corresponding to rows of the mapping table circuit. Each row of the mapping table circuit of the event mesh control circuit represents an implementation-specific grouping of events, with each column of the row representing a last known status or outcome for a corresponding event. A microcontroller of the serial protocol processor-based device is configured to use the register control array to select which event (i.e., which column of a corresponding row) will be used to make a branching determination. A branch custom instruction provided by the microcontroller indicates a selected row, a branch target address, and a comparison value to compare against the event indicated by the register control array entry corresponding to the selected row.

Abstract: Systems and methods for providing split read transactions over an audio communication bus are disclosed. In one aspect, a device that receives a read command informs a requester that data is not yet available and to try again at a future time, potentially outside the traditional response window. In the meantime, the receiving device begins fetching the requested data to have available when the requester makes a subsequent request. By providing a not yet response, data may be fetched from a memory element in a low-power state after it has been taken out of the low-power state or data may be fetched from a remote location or over a slow internal bus.

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

Abstract: The disclosure includes systems and methods for bus control. A method comprises receiving a data exchange request, wherein the data exchange request includes a data exchange tag that identifies a data exchange, splitting the data exchange into a plurality of fractional data transactions, providing one or more bus commands to a system bus, receiving, at the bus controller, one or more acceptance notifications indicating that the one or more of the plurality have been accepted by the system bus, assigning transaction identifiers (TIDs) corresponding to the one or more of the plurality of fractional data transactions, receiving one or more completion notifications indicating that the one or more of the plurality have been completed, determining that each of the plurality of fractional data transactions associated with the data exchange tag have been completed, and notifying the processor that the requested data exchange has been completed.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus having multiple data lanes includes providing a plurality of frames, each frame being configured to carry up to a maximum number of data bytes, transmitting a first frame over the serial bus, where the first frame is filled with first data bytes, notifying one or more devices of unavailability of an alert opportunity prior to transmitting the first frame, transmitting a second frame over the serial bus, where the first frame includes second data bytes less in number than the maximum number of data bytes, and notifying the one or more devices that the second frame provides an opportunity to launch an alert after transmission of the second data bytes.

Abstract: System, methods and apparatus are described that enable the reliable generation of pulses in a clock signal transmitted over an I3C bus. In various aspects of the disclosure, a method of data communications may be performed by a master device to generate a clock signal to be transmitted on a serial bus. The method includes calculating a divisor based on frequency of a first clock signal and duration of a first pulse to be transmitted in a second clock signal over a clock line of the serial bus, using the divisor to divide the first clock signal to obtain a divided clock signal, and generating the first pulse using the divided clock signal.

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described. A master device coupled to the serial bus may detect signaling on the serial bus corresponding to an in-band interrupt asserted by a slave device that is addressable by a first device identifier, receive a second device identifier transmitted by the slave device in relation to the in-band interrupt, use the second device identifier to select an execution environment, and interrupt the execution environment responsive to the in-band interrupt. The slave device may use the first device identifier in transactions conducted over the serial bus. After detecting an event generated by an event source, the slave device may initiate an in-band interrupt on the serial bus, and may transmit the second device identifier to indicate the event source during an in-band interrupt handling procedure.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. An apparatus has a bus including a first lane and a second lane, a plurality of devices coupled to the bus and, in a first mode of operation, the plurality of devices is configured to exchange data in a signal transmitted on the first lane in accordance with timing provided by a clock signal transmitted on the second lane. The apparatus may include one or more additional lanes connecting two or more devices in the plurality of devices, the two or more devices being configured to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a non-participating device to cause a master device on an I3C bus transmit a STOP condition that terminates a transaction with a slave device coupled to the I3C bus. A method performed at a master device coupled to a serial bus includes initiating a transaction between the master device and a first slave device, terminating the transaction before completion of the transaction when a second slave device intervenes in the transaction, and servicing the second slave device after terminating the transaction. The transaction may include transmissions of data frames over the serial bus. The second slave device may intervene when it is not a party to the transaction.

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.