Patents by Inventor Shen PING
Shen PING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901433Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.Type: GrantFiled: August 24, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20230005852Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11541358Abstract: A method for process a chemical liquid is provided. The method includes at least providing a system having at least one filtration medium, treatment the system with a treatment liquid having a content of iron (Fe) and calcium (Ca) of about 10 ppb or less, and processing a chemical liquid using an apparatus having the system configured therein after the treatment process.Type: GrantFiled: August 21, 2019Date of Patent: January 3, 2023Assignee: FUJIFILM Electronic Materials U.S.A., Inc.Inventors: Marcia Cole-Yocom, Bryan Hinzie, Michael Barker, Jack Helzer, Shen-Ping Huang, Pejman Ahmadiannamini, Yuan Chen
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Patent number: 11541335Abstract: A chemical liquid purification apparatus includes a tank body, a return tube, a liquid sending pump, a filtration device and a piping. The tank body has a liquid passage port and a circulation port communicated to a storage space inside the tank body. The return tube has one end connected to the circulation port and another end extending to the storage space. The liquid sending pump and the filtration device are located outside the tank body in between the liquid passage port and the circulation port. The piping is connecting the liquid sending pump and the filtration device to the liquid passage port and the circulation port.Type: GrantFiled: May 27, 2020Date of Patent: January 3, 2023Assignee: FUJIFILM Electronic Materials Taiwan Co., Ltd.Inventors: Kenichi Tanaka, Cheng-Chieh Fan, Shen-Ping Huang
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Publication number: 20220336631Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
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Patent number: 11444046Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: GrantFiled: August 27, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11374107Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.Type: GrantFiled: June 15, 2020Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20210384319Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.Type: ApplicationFiled: August 24, 2021Publication date: December 9, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
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Patent number: 11114543Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.Type: GrantFiled: March 16, 2017Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hong Chang, Chih-Yuan Chan, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
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Publication number: 20200395320Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20200376419Abstract: A chemical liquid purification apparatus includes a tank body, a return tube, a liquid sending pump, a filtration device and a piping. The tank body has a liquid passage port and a circulation port communicated to a storage space inside the tank body. The return tube has one end connected to the circulation port and another end extending to the storage space. The liquid sending pump and the filtration device are located outside the tank body in between the liquid passage port and the circulation port. The piping is connecting the liquid sending pump and the filtration device to the liquid passage port and the circulation port.Type: ApplicationFiled: May 27, 2020Publication date: December 3, 2020Applicant: FUJIFILM Electronic Materials Taiwan Co., Ltd.Inventors: KENICHI TANAKA, CHENG-CHIEH FAN, SHEN-PING HUANG
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Patent number: 10840371Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: GrantFiled: October 25, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
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Patent number: 10804231Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: GrantFiled: May 22, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20200312983Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
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Patent number: 10686054Abstract: A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.Type: GrantFiled: November 19, 2018Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20200066902Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: ApplicationFiled: October 25, 2019Publication date: February 27, 2020Inventors: Tsai-Feng YANG, Chih-Heng SHEN, Chun-Yi YANG, Kun-Ming HUANG, Po-Tao CHU, Shen-Ping WANG
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Publication number: 20200061544Abstract: A method for process a chemical liquid is provided. The method includes at least providing a system having at least one filtration medium, treatment the system with a treatment liquid having a content of iron (Fe) and calcium (Ca) of about 10 ppb or less, and processing a chemical liquid using an apparatus having the system configured therein after the treatment process.Type: ApplicationFiled: August 21, 2019Publication date: February 27, 2020Applicant: FUJIFILM Electronic Materials U.S.A., Inc.Inventors: Marcia Cole-Yocom, Bryan Hinzie, Michael Barker, Jack Helzer, Shen-Ping Huang, Pejman Ahmadiannamini, Yuan Chen
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Patent number: 10461183Abstract: A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
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Publication number: 20190273059Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: ApplicationFiled: May 22, 2019Publication date: September 5, 2019Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20190272008Abstract: A modular SSD inserts within a bay in a rack server that may also accommodate a standard modular HDD. The modular SSD includes first and second PCBs each having SSD modules mounted thereto. For example, four SSD modules on each PCB. The first PCB includes a data connector at a first end that connects to a connector at the first end of the second PCB. The second PCB includes one or more connectors at a second end, opposite the first, for connecting to the backplane of the rack server. The backplane is coupled to a motherboard within the rack server.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Inventor: Shen Ping