Patents by Inventor Sheng Chen

Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Patent number: 11985825
    Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Feng-Cheng Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 11983742
    Abstract: Systems, methods, and computer-readable media are disclosed for modeled advertisement conversion attributions. An example method may include receiving first input data comprising first advertisement impression data and first advertisement conversion data, wherein the first input data includes one or more user identifiers associated with both the advertisement impression data and advertisement conversion data. The example method may also include training one or more machine learning models using the first input data. The example method may also include receiving second input data comprising second advertisement impression data, wherein user identifiers are unavailable for the second input data. The example method may also include determining, using the one or more machine learning models, second predicted conversion data associated with the second input data.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: May 14, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Sheng Ma, Jia Chen, Hancheng Ge, Paula Despins
  • Patent number: 11984476
    Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11984353
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
  • Patent number: 11985263
    Abstract: An asynchronous and concurrent transaction processing method with high-performance oriented to a permissioned blockchain belongs to the field of blockchain technologies. The method designs two processing schemes for abort transactions, namely, additional submission of unnecessary abort transactions that are serializable and delayed centralized processing of long-conflict-chain transaction aggregation. In order to avoid the instability of system transaction processing performance caused by single point failure, the method designs a multi-node round robin consensus strategy. In addition, an inter-node auxiliary concurrency acceleration scheme is designed, which can improve the transaction performance of the whole of the system only by upgrading some of node devices in the system.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: May 14, 2024
    Assignee: TIANJIN UNIVERSITY
    Inventors: Xiulong Liu, Baochao Chen, Sheng Qin, Keqiu Li
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11980694
    Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Hung Chen, Chih-Wen Chiang, Yun-Tung Pai, Yen-Hua Hsiao, Yao-Kuang Su, Yi-Hsuan Lin, Han-Sheng Siao
  • Publication number: 20240155663
    Abstract: A radio resource allocation method and a radio resource allocation system are provided. The radio resource allocation method includes: obtaining quality parameters of each of resource blocks, in which the quality parameters correspond to weight coefficients, respectively; adjusting the weight coefficients for a service requirement of each of network slices, and calculating, according to the weight coefficients and the quality parameters of each of the resource blocks, priority indices used to allocate the resource blocks to the network slices, respectively; and generating priority orders for allocating the resource blocks to the network slices, and configuring the base station to allocate the resource blocks to the network slices according to the priority orders.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 9, 2024
    Inventors: CHENG-CHANG CHEN, LI-SHENG CHEN
  • Publication number: 20240152321
    Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Meng-Fan CHANG, Ping-Chun WU, Jin-Sheng REN, Li-Yang HONG, Ho-Yu CHEN
  • Publication number: 20240154021
    Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 9, 2024
    Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
  • Publication number: 20240153719
    Abstract: An operation-indication mode switching structure, a circuit, and a method for operating the same are provided. The operation-indication mode switching structure is disposed on a housing of a device, and includes a switching mechanism that is used to switch multiple operation-indication modes. The switching mechanism is selectively connected with one of multiple signal terminals. When the switching mechanism is manipulated to switch to one of the operation-indication modes, a control unit of the device receives an operation-indication mode switching signal generated by the switching mechanism conducting or circuit-shorting one of the multiple signal terminals. A corresponding operation-indication mode that is a covert mode, a stealth mode, or a normal mode can be determined. The control unit is used to control an indication function of the device according to the operation-indication mode that is switched to.
    Type: Application
    Filed: July 18, 2023
    Publication date: May 9, 2024
    Inventors: HSIEN-YANG CHIANG, TA-WEI CHANG, CHENG-LIANG HUANG, YEH-SHENG CHEN
  • Publication number: 20240153987
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20240155082
    Abstract: A body-worn camera and an operation method thereof are provided, and the body-worn camera a central processing unit, a video recording module, a turntable, and a main button. The video recording module is electrically connected to the central processing unit. The turntable is electrically connected to the central processing unit. The main button is electrically connected to the central processing unit. After the video recording module completes recording a video, when the central processing unit receives a category mode signal from the turntable and receives a category name confirmation signal from the main button, the central processing unit executes a video tagging program, and the video tagging program saves a corresponding relationship between a category name and the video.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 9, 2024
    Inventors: HSIEN-YANG CHIANG, TA-WEI CHANG, CHENG-LIANG HUANG, YEH-SHENG CHEN
  • Patent number: 11977609
    Abstract: A USB protocol-based IP infringement identification method for USB devices, including the following steps: S1, connecting an infringement identification device at a peer side of the USB host to be tested; S2, the USB host to be tested entering compliance mode; S3, the infringement identification device sending an X.LFPS file to the USB host to be tested; S4, upon the USB host to be tested receiving the X.LFPS file, the USB host to be tested sending IP copyright information to the infringement identification device; S5, determining whether the USB host to be tested infringes the IP. The infringement identification of the USB device to be tested is performed by using the compliance mode specified in the USB protocol, which is more stable, reliable and can also save costs.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 7, 2024
    Assignee: CORIGINE (SHANGHAI), INC.
    Inventors: Kai Cheng, Sheng Lu, YirngAn Chen, Xin Jiang, Xiao Xiao
  • Patent number: 11976018
    Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 7, 2024
    Assignee: DAXIN MATERIALS CORP.
    Inventors: Kai-Sheng Jeng, Yuan-Li Liao, You-Ming Chen, Yu-Ying Kuo, Shao-Chi Cheng
  • Patent number: 11976783
    Abstract: A mounting structure for connecting an electronic device to a mounting surface is provided. The mounting structure includes a mounting base, a linkage, and a bracket. The first end of the linkage pivots on the mounting base. The bracket is rotatably connected to the second end of the linkage, wherein the bracket includes a cable receiving groove. The electronic device is disposed on the bracket. The electronic device includes a cable. At least a portion of the cable extends into the cable receiving groove.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: May 7, 2024
    Assignee: WISTRON NEWEB CORP.
    Inventors: Yan-Da Chen, Bing-Sheng Hsieh
  • Patent number: 11978392
    Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 7, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Min-Yang Chiu, Yu-Sheng Ma, Jin-Yi Lin, Hsuan-Yu Chen, Jhih-Siou Cheng, Chun-Fu Lin
  • Publication number: 20240143005
    Abstract: A power supply suppression circuit (10), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit (10) comprises a sampling unit (105), a compensation unit (106), and an amplification unit (107). The sampling unit (105) is connected to the compensation unit (106), and the compensation unit (106) is connected to the amplification unit (107). The power supply suppression circuit (10) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Chunling LI, Yongshou WANG, Cheng CHEN, Sheng LIN
  • Publication number: 20240140765
    Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 2, 2024
    Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Caung-Yu Liu