Patents by Inventor Sheng Chen

Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168329
    Abstract: An electronic device including a first light emitting unit, a second light emitting unit, a first optical layer and a second optical layer is disclosed. The first light emitting unit emits a first light. The second light emitting unit emits a second light. At least one of the first light and the second light passes through the first optical layer. The second optical layer is overlapped with the first optical layer. The second optical layer is configured to scatter the first light emitted from the first light emitting unit. When the first light emitting unit emits the first light, the second light emitting unit selectively emits the second light.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: InnoLux Corporation
    Inventors: Kuei-Sheng CHANG, Kuo-Jung Wu, Po-Yang Chen, I-An Yao
  • Publication number: 20240168373
    Abstract: A photoresist composition includes a mixture. The mixture includes a first photosensitive material and a second photosensitive material. The first photosensitive material is a 6-Sn oxide cluster, a 12-Sn oxide cluster or a combination thereof. The second photosensitive material has a composition being different from a composition of the first photosensitive material.
    Type: Application
    Filed: June 13, 2023
    Publication date: May 23, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
    Inventors: Jui-Hsiung LIU, Tsai-Sheng GAU, Burn Jeng LIN, Yan-Ru WU, Ting-An LIN, Han-Tsung TSAI, Po-Hsiung CHEN
  • Publication number: 20240170613
    Abstract: An optoelectronic semiconductor element is provided. The optoelectronic semiconductor element includes a semiconductor stack and a first metal layer. The semiconductor stack includes a first portion and a second portion stacked in sequence, with the second portion including an active region. The first metal layer is located on the first portion and is electrically connected to the first portion. A top-view outline of the first portion shows a first pattern, a top-view outline of the second portion shows a second pattern, and a top-view outline of the first metal layer shows a third pattern. The area ratio of the third pattern to the first pattern is from 0.5% to 10%.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Inventors: Ching-En Huang, Chuang-Sheng Lin, Hao-Ming Ku, Shih-I Chen
  • Publication number: 20240170709
    Abstract: A motion synchronized multi-tier pallet rack and a battery formation apparatus are provided. The pallet rack includes a fixation rack, two movable frames, and two actuators. The movable frames are coupled to two corresponding sides of the fixation rack and each includes telescopic arms, a motor, and a drive rod. The actuators are disposed on other the two corresponding sides of the fixation rack to drive the movable frames to move toward or away from each other. The telescopic arms are kinematically connected to the motor through the drive rod to extend from or retract into the movable frame. The battery formation apparatus includes a motion synchronized multi-tier pallet rack, a conveyor module, a formation cabinet, and a controller. The conveyor module carries a battery module. The controller controls the pallet rack to obtain the battery module from the conveyor module and place the battery module in the formation cabinet.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 23, 2024
    Applicant: CHROMA ATE INC.
    Inventors: Ming-Cheng Huang, Jiun-Ren Chen, Chao-Cheng Wu, Yi-Sheng Hsu
  • Publication number: 20240170537
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20240167163
    Abstract: An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: May 23, 2024
    Inventors: YI LING CHEN, WEI TSE HO, CHIN-SHENG WANG, PU-JU LIN, CHENG-TA KO
  • Publication number: 20240170343
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Patent number: 11990182
    Abstract: An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Cheng-Hsien Wu, Yu-Sheng Chen, Elia Ambrosi, Chien-Min Lee, Xinyu Bao
  • Patent number: 11989424
    Abstract: The invention discloses a digital signature system. The digital signature system comprises an electronic device and a data storage device. The electronic device generates a specific data by executing a specific operation, and calculates the specific data via a hash algorithm to generate a hash data. The data storage device comprises a controller, a plurality of flash memories, and a data transmission interface. The electronic device transmits the hash data to the data storage device via the transmission interface. The controller comprises a firmware. The firmware reads an unclonable function, and generates a private key according to the unclonable function, and encrypts the hash data by the private key to obtain a digital signature. The data storage device transmits the digital signature to the electronic device via the transmission interface.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 21, 2024
    Assignee: INNODISK CORPORATION
    Inventors: Ming-Sheng Chen, Chin-Chung Kuo
  • Patent number: 11991886
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Bo-Feng Young, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20240164109
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 16, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240157412
    Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo Chen CHEN, Sheng-Wei Wu, Yung-Li Tsai
  • Publication number: 20240157063
    Abstract: A drug delivery device including a main housing and a drug delivery module is provided. The main housing has an internal space. The drug delivery module is disposed in the internal space so as to be isolated from an external environment. The drug delivery module includes a drug bottle that contains a liquid drug and a driver that is connected to the drug bottle. The driver is configured to push the liquid drug to pass through a drug nebulization structure of the drug bottle such that the liquid drug is nebulized into a nebulized drug.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Inventors: Chieh-Sheng Cheng, JUI-SHUI CHEN, YI-HUNG WANG
  • Publication number: 20240157548
    Abstract: A transition method of locomotion gait of a robot includes: executing a deployment procedure multiple times, each execution includes: randomly selecting a source policy and a destination policy, simulating a transition operation from the source policy to the destination policy, and recording a transition configuration and a transition result to a transition database, where each policy is a neural network model, and a latent state in the transition configuration is a hidden layer of the neural network model of the source policy. The method further includes: training a transition-net according to the transition database, and performing the following steps by a meta-controller disposed on the robot: selecting two gait policies as an active policy and a queued policy, executing the active policy, inputting the two policies to the transition-net to obtain a success probability, and when the success probability is greater than a threshold, executing the queued policy.
    Type: Application
    Filed: December 20, 2022
    Publication date: May 16, 2024
    Inventors: Guilherme Henrique Galelli Christmann, Jonathan Hans Soeseno, Ying-sheng Luo, Wei-Chao Chen
  • Publication number: 20240158968
    Abstract: A breathable and waterproof non-woven fabric is manufactured by a manufacturing method including the following steps. Performing a kneading process on 87 to 91 parts by weight of a polyester, 5 to 7 parts by weight of a water repellent, and 3 to 6 parts by weight of a flow promoter to form a mixture, in which the polyester has a melt index between 350 g/10 min and 1310 g/10 min at a temperature of 270° C., and the mixture has a melt index between 530 g/10 min and 1540 g/10 min at a temperature of 270° C. Performing a melt-blowing process on the mixture, such that the flow promoter is volatilized and a melt-blown fiber is formed, in which the melt-blown fiber has a fiber body and the water repellent disposed on the fiber body with a particle size (D90) between 350 nm and 450 nm.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Inventors: Ying-Chi LIN, Wei-Hung CHEN, Li-Chen CHU, Rih-Sheng CHIANG
  • Publication number: 20240162308
    Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.
    Type: Application
    Filed: February 9, 2023
    Publication date: May 16, 2024
    Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
  • Publication number: 20240160172
    Abstract: A highly integrated and smart control system includes a control module, a fan driver module, and a light driver module. The control module controls the fan driver module and/or the light driver module. The control module is a control chip packaged and integrated by a WiFi unit, a Bluetooth unit, and a central processing unit (CPU). The CPU receives signals from the WiFi unit and the Bluetooth unit and accordingly controls the fan driver module and/or the light driver module. The present invention is able to decrease control chips needed and simplify circuitry needed for controlling a ceiling fan with or without a pendant light attached. The present invention enables smart controls over the ceiling fan with or without the pendant light by only using a single control chip.
    Type: Application
    Filed: February 9, 2023
    Publication date: May 16, 2024
    Inventors: JIAN-SHENG ZHANG, ZI-JIAN CHEN
  • Publication number: 20240162814
    Abstract: A switch device includes a driver circuit, a switch circuit and a level transition circuit. The driver circuit includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first terminal coupled to a first reference terminal, and a second terminal coupled to a second reference terminal. The switch circuit includes a control terminal for receiving the output signal. The level transition circuit includes a first terminal for receiving the output signal, a second terminal coupled to a third reference terminal, and a third terminal for receiving the input signal. In a transition interval, the input signal is transitioned from a first input signal level to a second input signal level, the level transition circuit transitions the output signal from a first output signal level to a third output signal level between the first output signal level and a second output signal level.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 16, 2024
    Applicant: RichWave Technology Corp.
    Inventors: Hsien-Huang Tsai, Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 11985263
    Abstract: An asynchronous and concurrent transaction processing method with high-performance oriented to a permissioned blockchain belongs to the field of blockchain technologies. The method designs two processing schemes for abort transactions, namely, additional submission of unnecessary abort transactions that are serializable and delayed centralized processing of long-conflict-chain transaction aggregation. In order to avoid the instability of system transaction processing performance caused by single point failure, the method designs a multi-node round robin consensus strategy. In addition, an inter-node auxiliary concurrency acceleration scheme is designed, which can improve the transaction performance of the whole of the system only by upgrading some of node devices in the system.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: May 14, 2024
    Assignee: TIANJIN UNIVERSITY
    Inventors: Xiulong Liu, Baochao Chen, Sheng Qin, Keqiu Li
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung