Abstract: A LED driving method includes steps of: providing a first pulse width modulation (PWM) signal for determining a brightness of a LED; obtaining a duty cycle of the first PWM signal; and selectively enabling the LED to work with a PWM dimming mode or a direct current (DC) dimming mode according to a relative relationship between a magnitude of the obtained duty cycle and a preset threshold value. Since the LED is performed with a two stage brightness control by use of mixed dimming mode, the driving efficiency of the LED can be improved.

Abstract: The present invention relates to a gate driver circuit and application of the same in a liquid crystal display (LCD) for improving the display performance thereof. The gate driver circuit includes at least one PMOS transistor and two NMOS transistors configured to modify a falling edge of a corresponding scanning signal according to a linear function that defines a waveform shape for the scanning signal.

Abstract: A driving power control circuit and method for light emitting diodes (LEDs) are provided. The driving power control circuit includes a plurality of switch units and a control unit. Each switch unit is electrically coupled to one LED string whose end generates node voltage. The control unit includes a voltage selecting module, a subtractor, and an adjusting module. The voltage selecting module is electrically coupled to the node voltages and outputs one of the node voltages as a reference node voltage. The subtractor is electrically coupled to an output terminal of the voltage selecting module and generates a corresponding feedback voltage according to the reference node voltage and the node voltage. The adjusting module is electrically coupled to an output terminal of the subtractor and outputs a corresponding adjusting signal according to the feedback voltage to determine whether the corresponding switch unit is turned on.

Abstract: A control signal generation method of integrated gate driver circuit includes the steps of: providing one gate control signal to an integrated gate driver circuit; and generating a plurality of internal control signals by the integrated gate driver circuit according to on the gate control signal to control internal operations of the integrated gate driver circuit. Furthermore, an integrated gate driver circuit is adapted to receive one external gate control signal. The integrated gate driver circuit includes an internal control signal generation circuit for generating a plurality of internal control signals according to the external gate control signal to control internal operations of the integrated gate driver circuit. In addition, a liquid crystal display device using the above-mentioned integrated gate driver circuit also is provided.

Abstract: A display panel including a liquid crystal layer, several driving circuits, several flexible circuit films and at least one printed circuit board is provided. The liquid crystal layer is disposed between a first substrate and a second substrate, wherein the first substrate has a display area and at least one peripheral area adjacent to the display area, the second substrate has at least one common electrode. The driving circuits are disposed on the peripheral area in series. The flexible circuit films are electrically connected to the driving circuits. The printed circuit board is electrically connected to the flexible circuit films, so as to transmit at least two different common voltages to a portion of the common electrode via the flexible circuit films.

Abstract: A driving apparatus for driving a liquid crystal display panel includes a timing controller, a plurality of pairs of transmission lines, a plurality of source driving circuits, a plurality of terminal resistors, and a plurality of auxiliary resistors. The timing controller functions to generate a plurality of differential signals outputted via a plurality of output ports. Each output port includes two output ends for outputting a corresponding differential signal. Each pair of transmission lines is coupled to the timing controller for receiving a corresponding differential signal. Each source driving circuit is coupled to the pairs of transmission lines for receiving the differential signals so as to generate a plurality of data signals. Each terminal resistor is coupled between two terminals of a corresponding pair of transmission lines. Each auxiliary resistor is coupled between two output ends of a corresponding output port of the timing controller.

Abstract: A method for express execution of internet service accessing with a touch-control interface for a computer system is provided. A computer system is installed with a first operating system in a data storage therein. The method includes the following steps: the computer system executing the BIOS of the computer system; before loading and executing the first operating system, the computer system detecting and activating a touch-control display device; the touch-control display device displaying executive item icons representing internet service accessing programs; detecting the executive item icon selection by the user; based on the selection, loading and executing the first operating system; and executing the internet service accessing program corresponding to the selected executive item icon.

Abstract: A method for express execution of navigation function is provided. A computer system is installed with a first operating system in a data storage device therein. The method includes the following steps: the computer system executing the BIOS of the computer system; before loading and executing the first operating system, the computer system detecting and activating a touch-control display device; the touch-control display device displaying an executive item icon representing the navigation function; detecting the executive item icon selection by the user; based on the selection, loading and executing the first operating system; and executing the navigation function corresponding to the selected executive item icon.

Abstract: A source driver comprising a first DAC with a positive polarity (PDAC), a second DAC with a negative polarity (NDAC), first and second operational amplifiers. Each operational amplifier is characterized with a 1st & 2nd stage and an output stage. The PDAC and NDAC are coupled to the first and second operational amplifiers through a first pair of switches. The 1st & 2nd and output stages of the first operational amplifier are coupled to the 1st & 2nd and output stages of the second operational amplifier through a second pair of switches. The first and second operational amplifiers are coupled to odd data lines and even data line through a third pair of switches.

Abstract: A driving circuit includes a power supply, a plurality of conductive paths and a plurality of driving controller. The power supply is configured for providing a predetermined voltage. The conductive paths are connected to the power supply to receive the predetermined voltage. The driving controllers are connected to the conductive paths correspondingly. A first driving controller of the driving controllers has a first internal circuit configured for employing an internal voltage to perform functions provided by the first driving controller, and a resistance adjustment unit. The resistance adjustment unit is connected between a special conductive path and the first internal circuit. The second driving controller has a second internal circuit configured for employing a second internal voltage to perform functions provided by the second driving controller. A resistance value of the resistance adjustment unit is adjustable to make the first internal voltage same to the second internal voltage.

Abstract: A driving apparatus for a liquid crystal display (LCD) is provided. The driving apparatus includes a plurality of data driving ICs and a control board. The data driving ICs are used for receiving and transmitting a clock signal, a plurality of data signals and a first reference voltage from the 1st data driving IC to the last data driving IC in series. The control board is used for providing the clock signal, the data signals and the first reference voltage, and changing the first reference voltage received by each data driving IC according to a variation of the clock signal and the data signals transmitted between the data driving ICs, so that the operation frequency of the data driving ICs is unrestricted.

Abstract: A driver integrated circuit chip adapted to electrically couple with a fan-out wiring area includes a side and a plurality of output pins formed at the side. The output pins includes a first pin group and a second pin group. The first pin group is electrically coupled to the fan-out wiring area. The second pin group is located at at least one side of the first pin group and opened. The present invention also provides display substrates of flat panel display each adapted to electrically couple with a plurality of driver integrated circuit chips.

Abstract: A lighting apparatus having high operation reliability includes a first lighting unit with a first turn-on voltage and a second lighting unit with a second turn-on voltage greater than the first turn-on voltage. The lighting apparatus is put in use for generating output light according to a driving current flowing through the first lighting unit or the second lighting unit. The first lighting unit is capable of generating output light having a first brightness according to the driving current. The second lighting unit, electrically connected in parallel with the first lighting unit, is capable of generating output light having a second brightness according to the driving current. The second brightness is preferably identical to the first brightness.

Abstract: A driving power control circuit and method for light emitting diodes (LEDs) are provided. The driving power control circuit includes a plurality of switch units and a control unit. Each switch unit is electrically coupled to one LED string whose end generates node voltage. The control unit includes a voltage selecting module, a subtractor, and an adjusting module. The voltage selecting module is electrically coupled to the node voltages and outputs one of the node voltages as a reference node voltage. The subtractor is electrically coupled to an output terminal of the voltage selecting module and generates a corresponding feedback voltage according to the reference node voltage and the node voltage. The adjusting module is electrically coupled to an output terminal of the subtractor and outputs a corresponding adjusting signal according to the feedback voltage to determine whether the corresponding switch unit is turned on.

Abstract: The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge.

Abstract: A source driver comprising a first DAC with a positive polarity (PDAC), a second DAC with a negative polarity (NDAC), first and second operational amplifiers. Each operational amplifier is characterized with a 1st & 2nd stage and an output stage. The PDAC and NDAC are coupled to the first and second operational amplifiers through a first pair of switches. The 1st & 2nd and output stages of the first operational amplifier are coupled to the 1st & 2nd and output stages of the second operational amplifier through a second pair of switches. The first and second operational amplifiers are coupled to odd data lines and even data line through a third pair of switches.

Abstract: A driving circuit for driving a display panel comprising: (i) a printed circuit board, (ii) an input interface to receive input video signal, (iii) a timing controller to control timing signal for the display panel, (iv) a plurality of first source drivers, and (v) at least one second source driver, and wherein the display cells connected to the i-th data line and the (2j+1)-th or (2j+2)-th gate line, where j=0, 2, 4, . . . , <[Y/2], and i=1, 2, . . . , M, where Y and M are positive integers, receive data signals from corresponding data lines 1 through M, respectively, and the display cells connected to the (i+1)-th data line and the (2j+1)-th or (2j+2)-th gate line, where j=1, 3, . . . , <[Y/2]+1, and i=1, 2, . . . , M, receive shifted data signals from the data lines 2 through M+1, respectively.

Abstract: A repair line framework of liquid crystal display is provided. By disposing part of the repair line inside the integrated circuit chip so that the routing of part of the repair line will penetrate through the integrated circuit chip before returning to the panel, or by routing part of the repair line disposed on the substrate within the display region so that the routing is positioned under the black matrix of the color filter, the routing length of the repair line is shortened and the impedance of the repair line is reduced.

Abstract: A display IC chip includes a plurality of sides, a plurality of output terminals, two first color short-circuit lines, one second color short-circuit line, one third color short-circuit line, and conductive wires. The two first color short-circuit lines are parallel disposed in the IC chip and coupled to a first output terminal group of the output terminals. The second color short-circuit line is disposed between and parallel with the first color short-circuit lines. The second color short-circuit line is coupled to a second output terminal group of the output terminals. The third color short-circuit line is disposed between and parallel with the first color short-circuit lines. The third color short-circuit line is coupled to a third output terminal group of the output terminals. The conductive wires are coupled the first color short-circuit lines with the first output terminal group do not cross the second and third color short-circuit lines.

Abstract: The present invention in one aspect relates to a source driver comprising a first digital-to-analog converter with a positive polarity (PDAC), a second digital-to-analog converter with a negative polarity (NDAC), a first operational amplifier and a second operational amplifier. Each operational amplifier is characterized with a 1st & 2nd stage and an output stage. Both the PDAC and NDAC are coupled to the first and second operational amplifiers through a first pair of switches. The 1st & 2nd and output stages of the first operational amplifier are coupled to the 1st & 2nd and output stages of the second operational amplifier through a second pair of switches. The first and second operational amplifiers are coupled to odd data lines and even data line through a third pair of switches. Further, the amplitudes of the operational voltages for the PDAC, the NDAC and the output stages first and second operational amplifiers are set to be between the supply voltage and the ground voltage.