Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: Disclosure regards a signal conversion device and method and an analog-to-digital converter, including a channel module including a plurality of sampling channels, wherein each of the plurality of sampling channels is configured to receive an analog signal; a timing-control module configured to provide a plurality of candidate sequences including a first sequence and a second sequence for the same sampling channel, wherein the timing-control module sets a first sampling time corresponding to the first sequence and a second sampling time corresponding to the second sequence; a conversion module electrically coupled to the timing-control module and the channel module, wherein the conversion module is configured to convert the analog signal from the same sampling channel into a digital signal in response to an order and sampling times defined by the candidate sequences. Therefore, problems of poor sampling accuracy and flexibility in the current sampling technologies are effectively solved.

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: An electronic shelf label positioning system, an electronic shelf label and a guide rail. The electronic shelf label positioning system includes the electronic shelf label, the guide rail, a PDA and a background server. The electronic shelf label includes a main control SoC, a card reader IC, a screen and a power supply device. The main control SoC is configured to control the screen display and to communicate with an AP. The power supply device is configured to supply power to the electronic shelf label. The guide rail includes a guide rail identification area and a label area. The label area is installed with a plurality of wireless labels each having a unique non-repeated ID number. The guide rail identification area is installed with an identity recognition device, which includes a guide rail ID consisting of the ID numbers of the wireless labels sequentially arranged and summarized.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.

Abstract: An ORing FET control circuit and method are provided. The circuit includes an ORing FET, a comparator, first, second and third resistors, a first capacitor, a diode and a driving unit. The positive and negative input terminals of the comparator are electrically connected to the input and output voltages. The first resistor, the second resistor, the first capacitor, and the third resistor are electrically connected in series between a reference voltage and a ground terminal sequentially. The reference voltage is lower than a voltage at the positive input terminal. When the input voltage is lower than the output voltage, if a voltage across the ORing FET is larger than a threshold, the comparator outputs a driving signal at low level, and correspondingly the driving unit turns off the ORing FET. The threshold depends on resistances of the first and second resistors.

Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.

Abstract: A totem-pole PFC circuit and a control method thereof are provided. The circuit includes an AC power source, first and second bridge arms and a controller. The first bridge arm includes first and second switches electrically connected in series with a connection node electrically connected to a first terminal of the AC power source. The second bridge arm includes third and fourth switches electrically connected in series with a connection node electrically connected to a second terminal of the AC power source. When a potential at the first terminal is higher than a potential at the second terminal, the controller turns off the fourth switch if the L-phase voltage is lower than a first threshold voltage. When the potential at the first terminal is lower than the potential at the second terminal, the controller turns off the third switch if the L-phase voltage is higher than a second threshold voltage.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) region disposed over a substrate, a second S/D region disposed over the substrate, a dielectric wall disposed between the first and second S/D regions, a first conductive contact disposed over and electrically connected to the first S/D region, a second conductive contact disposed over and electrically connected to the second S/D region, and a first dielectric material in contact with the dielectric wall. The first dielectric material has a top surface located at a first level between a top surface of the first conductive contact and a bottom surface of the first conductive contact, and the first dielectric material extends from the first level to a second level located below the bottom surface of the first conductive contact.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.

Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: Provided are Enterococcus lactis, a drug for preventing or treating tumor, and use thereof, relating to the technical field of biomedicines. Novel Enterococcus lactis is separated and chosen, and the Enterococcus lactis has an important influence on the effect of tumor immunotherapy for cancer patients. Gut microorganisms and immune cells can interact with each other to jointly regulate the human immune system. The provided Enterococcus lactis can induce the differentiation and maturation of iDC (immature DC) cells, and mature DC can effectively activate T cells and increase the infiltration of tumor infiltrating lymphocytes having anti-tumor activity, thereby killing tumor cells. In addition, the provided Enterococcus lactis can induce the differentiation of M0 type macrophages into M1 or M2 type cells.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: According to the present disclosure, a measuring method of liquid mixture purity includes steps as follows. A storage tank is provided, wherein the storage tank is configured for storing a liquid mixture including formic acid and water. A calculating unit is provided, wherein a plurality of formic acid purity values are saved in the calculating unit. A pressure-decreasing and heating step is performed by reducing a pressure of the storage tank and heating the storage tank. A measuring step is performed by measuring in the inner space of the storage tank to obtain a pressure value, and measuring the liquid mixture simultaneously to obtain a temperature value. A calculating step is performed by inputting the pressure value and the temperature value into the calculating unit, wherein the calculating unit outputs one of the formic acid purity values corresponding thereto.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.