Abstract: Provided are Enterococcus lactis, a drug for preventing or treating tumor, and use thereof, relating to the technical field of biomedicines. Novel Enterococcus lactis is separated and chosen, and the Enterococcus lactis has an important influence on the effect of tumor immunotherapy for cancer patients. Gut microorganisms and immune cells can interact with each other to jointly regulate the human immune system. The provided Enterococcus lactis can induce the differentiation and maturation of iDC (immature DC) cells, and mature DC can effectively activate T cells and increase the infiltration of tumor infiltrating lymphocytes having anti-tumor activity, thereby killing tumor cells. In addition, the provided Enterococcus lactis can induce the differentiation of M0 type macrophages into M1 or M2 type cells.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.

Abstract: According to the present disclosure, a measuring method of liquid mixture purity includes steps as follows. A storage tank is provided, wherein the storage tank is configured for storing a liquid mixture including formic acid and water. A calculating unit is provided, wherein a plurality of formic acid purity values are saved in the calculating unit. A pressure-decreasing and heating step is performed by reducing a pressure of the storage tank and heating the storage tank. A measuring step is performed by measuring in the inner space of the storage tank to obtain a pressure value, and measuring the liquid mixture simultaneously to obtain a temperature value. A calculating step is performed by inputting the pressure value and the temperature value into the calculating unit, wherein the calculating unit outputs one of the formic acid purity values corresponding thereto.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: Embodiments of the present disclosure is directed to a method of controlling screen color temperature. The method includes: acquiring ambient light parameters according to a preset time interval, obtaining an ambient relative color temperature value corresponding to the ambient light parameter acquired at each acquisition time point, performing a weighted average process on the ambient relative color temperature value corresponding to the ambient light parameter acquired at each acquisition time point to obtain a target ambient color temperature value, determining a target screen color temperature value corresponding to the target ambient color temperature value and further a current screen color temperature value, and changing a color temperature value of the screen from the current screen color temperature value to the target screen color temperature value according to the screen color temperature value change time.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: A horizontally oriented calibration jig for a wafer gripper arm of an ion implanter is disclosed. The calibration jig is mounted within the process chamber of the ion implanter. The calibration jig includes a mounting plate that spans a diameter of the wafer gripper arm, a support stand passing through the mounting plate, and a calibration plate at a bottom end of the support stand. The perimeter of the calibration plate includes a plurality of notches. The calibration plate is rotated. If any finger of the wafer gripper arm falls into a notch, the rotating calibration plate stops. The finger is then adjusted until it does not fall into a notch.

Abstract: A thermal module may include a cold plate including a cold plate base having a cold plate base protruding portion, and a cold plate cover on the cold plate base, and a heat pipe between the cold plate base and the cold plate cover, and including an upper heat pipe portion and a lower heat pipe portion in the cold plate base protruding portion.

Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores an extreme memory profile (XMP). When the processor performs the BIOS so that the computer device displays a user interface (UI), the BIOS displays an overclocking option corresponding to the XMP in a selection list of the UI. When the BIOS receives a selection request corresponding to the overclocking option of the selection list, the BIOS reads multiple memory setting parameters corresponding to the XMP, and configures the memory module according to the memory setting parameters.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes first and second gate structures formed over a semiconductor substrate and a multilayer gate isolation structure separating the first gate structure from the second gate structure. The multilayer gate isolation structure includes a first insulating feature adjacent to upper portions of the first gate structure and the second gate structure, and a second insulating feature separating the semiconductor substrate from the first insulating feature. The material of the second insulating feature is different than that of the first insulating feature. The second insulating feature has a lower dielectric constant or lower etch resistance than the first insulating feature.

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Abstract: A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.