Patents by Inventor Sheng Liang

Sheng Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of manufacture
    Patent number: 10991805
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Online reordering of database table columns
    Patent number: 10990571
    Abstract: Online reordering for database table columns may allow a user to reorder the columns of a database table without taking the database offline. A mapping between different column orders for a database table may be generated and stored in response to a request to reorder columns in a database table. When a portion of the database table is accessed, the columns of the database table in the accessed portion of the database table may be reordered to perform the access request.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 27, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Zhaohui Zhang, Sheng-Liang Song, Aakash Shah, Kamal Kant Gupta, Xiaofeng Bao, Saileshwar Krishnamurthy
  • Semiconductor Device Structure Having a Plurality of Threshold Voltages and Method of Forming the Same
    Publication number: 20210119033
    Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Yu-San Chien, Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Fin Field-Effect Transistor Device and Method
    Publication number: 20210104443
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan
  • Method for manufacturing semiconductor device
    Patent number: 10971606
    Abstract: A method for manufacturing a semiconductor device includes forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins; forming a dummy gate layer over the STI structure and the semiconductor fins; etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, in which the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins; forming an insulating structure in the trench through the dummy gate layer; after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and replacing the dummy gate structures with a pair of metal gate structures.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Kuo-Hua Pan
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210098312
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Hsin-Che CHIANG, Yu-San CHIEN, Ta-Chun LIN, Chun-Sheng LIANG, Kuo-Hua PAN
  • CMOS finFET with doped spacers and method for forming the same
    Patent number: 10964815
    Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hong-Nien Lin, Ming-Heng Tsai, Yong-Yan Lu, Chun-Sheng Liang, Jeng-Ya Yeh
  • Epitaxial Blocking Layer for Multi-Gate Devices and Fabrication Methods Thereof
    Publication number: 20210082686
    Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
  • Semiconductor Device and Method
    Publication number: 20210082768
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • SEMICONDUCTOR PACKAGE HAVING LIQUID-COOLING LID
    Publication number: 20210074608
    Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.
    Type: Application
    Filed: August 11, 2020
    Publication date: March 11, 2021
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Sheng-Liang Kuo, Bo-Jiun Yang
  • Method and apparatus for surface and ambient temperature estimation for portable devices
    Patent number: 10942067
    Abstract: The surface temperature of a portable device is estimated. The portable device includes a sensor for detecting the internal temperature of the portable device. The portable device also includes circuitry for estimating the surface temperature, using the internal temperature and an ambient temperature of the portable device as input to a circuit model. The circuit model describes thermal behaviors of the portable device. The circuitry is operative to identify a scenario in which the portable device operates, and determine the ambient temperature using the scenario and at least the internal temperature.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: March 9, 2021
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, Pei-Yu Huang, Sheng-Liang Kuo, Jih-Ming Hsu, Tai-Yu Chen, Yun-Ching Li, Wei-Ting Wang
  • Semiconductor Device Structure With Uniform Threshold Voltage Distribution And Method Of Forming The Same
    Publication number: 20210066476
    Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
    Type: Application
    Filed: July 10, 2020
    Publication date: March 4, 2021
    Inventors: Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang, Kuo-Hua Pan
  • Reaction chamber for vapor deposition apparatus
    Patent number: 10927456
    Abstract: A reaction chamber for vapor deposition apparatus, comprises a susceptor to carry substrates, a ceiling, an upper cavity, and protrusions. The ceiling comprises a front surface faces the substrates and comprises front convex parts and front concave parts with an interlaced arrangement to form a convex-concave surface. The ceiling also comprises a rear surface opposites to the front surface and comprises rear convex parts and rear concave parts corresponded to the front concave parts and the front convex parts respectively. The upper cavity opposites to the rear surface and separated to the rear convex parts to define a first flow channel. The protrusions are disposed in the rear concave parts and separated to a side wall and a bottom wall of the rear concave parts to define a second flow channel which is connected to the first flow channel to introduce a cooling fluid.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 23, 2021
    Assignee: HERMES-EPITEK CORP.
    Inventors: Yu-Sheng Liang, Chien-Chin Chiu, Tsan-Hua Huang, Oishi Takahiro, Suda Noboru, Komeno Junji
  • Memory clock frequency adjusting method, mainboard, and computer operating system
    Patent number: 10922261
    Abstract: A memory clock frequency adjusting method suitable for a computer device is provided. The computer device includes a basic input output system (BIOS) and a memory. The memory clock frequency adjusting method includes following steps. A boot process of the computer device is executed, and the memory is operated at a memory clock frequency set by the BIOS. Whether the computer device is successfully booted is determined by the BIOS to decide whether the boot process of the computer device is to be re-executed. A setting of the memory clock frequency is adjusted by the BIOS when the computer device re-executes the boot process to lower the memory clock frequency, so that the memory is operated at the lowered memory clock frequency. In addition, a mainboard and a computer operating system applying the memory clock frequency adjusting method are also provided.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 16, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Cho-May Chen, Hou-Yuan Lin, Sheng-Liang Kao
  • METHOD FOR MANUFACTURING CAPACITIVE TOUCH CONTROL PANEL AND CAPACITIVE TOUCH CONTROL PANEL
    Publication number: 20210019002
    Abstract: A method for manufacturing capacitive touch control panel and a capacitive touch control panel are provided. The method includes forming a sensing circuit on a substrate and then forming a communicating structure on the substrate. The communicating structure is conductive, and is disposed to be near at least two adjacent side walls of the substrate. A gap is formed between the communicating structure and the plurality of the sensing electrodes that are near the communicating structure. The next step is to form a plurality of bridging structures for connecting the plurality of the sensing electrodes and the communicating structure. The last step is to remove a portion of the communicating structure by laser cutting to form a plurality of output cables.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: CHUN-WEI YEH, SHENG-LIANG LIN, YI-HAN WANG, HUNG-YU TSAI
  • TOUCH SENSING SYSTEM AND DISPLAY SYSTEM INCLUDING THE SAME
    Publication number: 20210019034
    Abstract: A touch sensing system is provided. The touch sensing system includes a touch panel including touch sensors arranged in a grid along row and column directions; a touch controller including at least one transmission circuit to transmit a signal to the touch sensors and at least one reception circuit to detect a signal from the touch sensors; and a switching circuit to selectively connect each of the touch sensors to the at least one transmission circuit and the at least one reception circuit in accordance with an operation mode. The switching circuit connects each of the touch sensors to the at least one reception circuit in a touch mode and connects a first portion of the touch sensors to the at least one reception circuit and a second portion of the touch sensors to the at least one transmission circuit in a proximity mode.
    Type: Application
    Filed: March 18, 2020
    Publication date: January 21, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsung KIM, Sanho Byun, Roots Huang, Yao Sheng Liang, Jungmoon Kim, Dongjo Park
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210013205
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
  • Inorganic shell, resin composition, and method for making inorganic shell
    Patent number: 10875984
    Abstract: An inorganic shell is ball-shaped and hollow, and includes silica and crystalline inorganic powder sintered together. A resin composition has the inorganic shells and the resin composition has certain dieletric characteristics. A method for making the inorganic shell is also provided.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 29, 2020
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Kuo-Sheng Liang, Shou-Jui Hsiang, Mao-Feng Hsu, Hong-Ping Lin
  • Methods of fabricating semiconductor devices having gate structure with bent sidewalls
    Patent number: 10879393
    Abstract: A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Jeng-Ya Yeh
  • Rectifier unit of AC generator
    Patent number: D908086
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 19, 2021
    Assignee: Victory Industrial Corporation
    Inventors: Hung-Chih Chang, Fu-Sheng Liang