Abstract: An operation voltage testing circuit includes a voltage generating circuit, a current-to-voltage conversion circuit, and a processing circuit. The voltage generating circuit is configured to generate a first voltage signal according to a first current signal, such that a photoelectric conversion unit generates a second current signal corresponding to the first voltage signal. The current-to-voltage conversion circuit is configured to generate a second voltage signal corresponding to the second current signal. The processing circuit is configured to receive the second voltage signal and to selectively adjust and output the first current signal according to the second voltage signal and a threshold value, such that the voltage generating circuit selectively adjusts the first voltage signal according to the first current signal.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Abstract: A lifting mechanism is adapted to bear an expansion unit, and the expansion unit contacts or is separated from a heat dissipating module. The lifting mechanism includes an outer casing base and a bearing base. The bearing base is disposed on the outer casing base liftably along a first axis. The expansion unit is disposed on the bearing base. When the bearing base is located at an original position relative to the outer casing base, the expansion unit on the bearing base is separated from the heat dissipating module. When the bearing base is lifted relative to the outer casing base along the first axis to a lifting position, the expansion unit on the bearing base contacts the heat dissipating module. An electronic device having the lifting mechanism is further provided.

Abstract: A method of treating a subject suffering from an angiogenesis-related disease, which is implemented by administering to the subject a pharmaceutical composition comprising a compound of formula I derived from Mitella formosana to inhibit the angiogenic function of endothelial progenitor cells.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Abstract: A FinFET device includes a fin structure, a gate structure, a gate helmet, a pair of spacers and a contact structure. The fin structure protrudes from a semiconductor substrate. The gate structure crosses over the fin structure. The gate helmet includes a base and a pair of fringes. The base is disposed on a top surface of the gate structure. The pair of fringes is extended upwards from opposite sides of the base. The pair of spacers is positioned on the pair of the fringes. The contact structure is disposed between the pair of the fringes and between the pair of the spacers.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.

Abstract: A low dropout regulator includes a PMOS power transistor, a feedback network, an error amplifier and an active enhanced PSRR unit. The PMOS power transistor has a first end coupled to an input voltage, and a second end coupled to a load and the feedback network. The error amplifier receives a feedback signal generated from the feedback network, compares the feedback signal with a reference voltage to generate a difference value, and amplifies the difference value to generate an error signal. The active enhanced PSRR unit has one end coupled to the first end, and another end coupled to a control end of the PMOS power transistor and the error amplifier, detects an input voltage of the first end, and correspondingly adjusts a voltage of the control end to stabilize a voltage between the control end and the first end according to a variation of the input voltage.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Abstract: An impedance matching circuit includes a variable impedance circuit, a reference voltage generating circuit and a control circuit. The variable impedance circuit is configured for coupling to a load having an impedance and has a variable impedance; the reference voltage generating circuit coupled to the variable impedance circuit is configured to receive an input voltage of the variable impedance circuit to generate a reference voltage; and the control circuit coupled to the variable impedance circuit and configured to generate a control signal according to the reference voltage and an output voltage of the variable impedance circuit to control the variable impedance to make the variable impedance match the impedance of the load.

Abstract: A power supply system and a power supply method are provided. The power supply system includes a target device, a power supplier module and a control circuit. The control circuit is coupled to the target device and the power supplier module. The control circuit transmits a power provided by the power supplier module to the target device and disables a sub-target device of the target device if the power supplier module does not meet a default condition. The control circuit transmits the power provided by the power supplier module to the target device and enables the sub-target device if the power supplier module meets the default condition.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Abstract: A biasing voltage generating circuit for generating a required reverse biasing voltage of an avalanche photodiode (APD) includes: a boost power converter configured to operably convert an input voltage into a higher output voltage according to a feedback signal and a reference signal, and to apply the output voltage to be a reverse biasing voltage of the APD; a reference signal generating circuit configured to operably generate the reference signal; and a control circuit. The control circuit includes: a signal sensing circuit configured to operably generate a sensed signal corresponding to an output current of the APD; an analog-to-digital converter (ADC) configured to operably convert the sensed signal into a digital signal; and a processing circuit configured to operably adjust the feedback signal or the reference signal according to the digital signal to thereby control the boost power converter to adjust the output voltage.

Abstract: A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant.

Abstract: The invention relates to a use of an aurantiamide dipepetide derivative in the treatment or prevention of angiogenesis-related diseases. Accordingly, aurantiamide dipeptide derivatives can be used as angiogenesis inhibitor, whereby preventing or treating invasive and metastatic cancer and ocular neovascularization (particularly macular degeneration such as pathological neovascularization of age-related macular degeneration (AMD)).

Abstract: An operation voltage testing circuit includes a voltage generating circuit, a current-to-voltage conversion circuit, and a processing circuit. The voltage generating circuit is configured to generate a first voltage signal according to a first current signal, such that a photoelectric conversion unit generates a second current signal corresponding to the first voltage signal. The current-to-voltage conversion circuit is configured to generate a second voltage signal corresponding to the second current signal. The processing circuit is configured to receive the second voltage signal and to selectively adjust and output the first current signal according to the second voltage signal and a threshold value, such that the voltage generating circuit selectively adjusts the first voltage signal according to the first current signal.

Abstract: A channel detection method for an echo canceller of a communication device is provided. The method includes the following steps. A first detection signal is transmitted to an end of a channel coupled to the communication device. A plurality of taps corresponding to a reflected signal of the first detection signal are received by an echo canceller at the end of the channel. The taps corresponding to the reflected signal are compared with a reference value corresponding to each of the taps so as to determine whether each of the taps is larger than or equal to the corresponding reference value. When the tap is determined to be larger than or equal to the reference value corresponding to the tap, the tap and a position of the tap are recorded.

Abstract: A low dropout regulator includes a PMOS power transistor, a feedback network, an error amplifier and an active enhanced PSRR unit. The PMOS power transistor has a first end coupled to an input voltage, and a second end coupled to a load and the feedback network. The error amplifier receives a feedback signal generated from the feedback network, compares the feedback signal with a reference voltage to generate a difference value, and amplifies the difference value to generate an error signal. The active enhanced PSRR unit has one end coupled to the first end, and another end coupled to a control end of the PMOS power transistor and the error amplifier, detects an input voltage of the first end, and correspondingly adjusts a voltage of the control end to stabilize a voltage between the control end and the first end according to a variation of the input voltage.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.