Abstract: An impedance adjustment method for a communication device, wherein the communication device has a plurality of impedance paths for selection, includes: selecting an initial impedance path; and utilizing a predetermined algorithm to examine a portion of the plurality of impedance paths by starting from the initial impedance path for selecting an optimized impedance path for the communication device. A delay capacitance adjustment method for a communication device, wherein the communication device has a plurality of delay capacitance paths for selection, includes: selecting an initial delay capacitance path; and utilizing a predetermined algorithm to examine a portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting an optimized delay capacitance path of the communication device.

Abstract: The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and an parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K?1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least ?K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value.

Abstract: A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant.

Abstract: A current mode buck-boost converter has an input terminal, an output terminal, and an output capacitor coupled to the output terminal. The input terminal is used to receive an input voltage, and the output terminal is for producing the output voltage. The current mode buck-boost converter comprises a voltage converter and a control circuit. The voltage converter comprises an inductor. The control circuit is for detecting the current passing through the inductor to determine the electric energy transmitted to the output terminal by the voltage converter. Accordingly, the current mode buck-boost converter has fast response, and the electrical energy can be recycled and stored to the voltage source when the current mode buck-boost converter operates in down-tracking process.

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.

Abstract: A power management method for a health care device is included. The method includes: detecting whether a smart garment is in contact with a user body; operating the health care device in a normal mode when the smart garment is in contact with the user body, or operating the health care device in a low-power mode when the smart garment is not in contact with the user body; and under the low-power mode, detecting whether the health care device is tapped to determine whether to transmit user health data to a user device.

Abstract: A voltage regulating apparatus is disclosed. The voltage regulating apparatus includes: a power transistor having a control terminal, a first terminal for receiving a power supply, and a second terminal for providing an output voltage; a feedback circuit coupled to the second terminal, configured for providing a feedback voltage according to the output voltage; an amplifier having a source current unit and a sink current unit, configured for driving the power transistor through the control terminal by use of the source and sink current units according to a reference voltage and the feedback voltage; and a transient enhancement unit configured for monitoring the source and sink current units, and regulating a voltage at the control terminal according to the monitored result.

Abstract: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Abstract: A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.

Abstract: A capacitance sensing circuit for a touch panel includes an analog capacitance-detecting circuit, a PWM-to-digital circuit and a self-calibration circuit. The analog capacitance-detecting circuit detects the capacitance of the touch panel based on a charging current, and converts the detected capacitance into a PWM control signal. The PWM-to-digital circuit converts the PWM control signal into a sensing count value based on a clock signal. The self-calibration circuit adjusts the value of the charging current or the frequency of the clock signal according to the difference between the range of the sensing count value and a predetermined detecting range. The predetermined detecting range can thus be adjusted for matching the range of the sensing count value.

Abstract: A current mode buck-boost converter has an input terminal, an output terminal, and an output capacitor coupled to the output terminal. The input terminal is used to receive an input voltage, and the output terminal is for producing the output voltage. The current mode buck-boost converter comprises a voltage converter and a control circuit. The voltage converter comprises an inductor. The control circuit is for detecting the current passing through the inductor to determine the electric energy transmitted to the output terminal by the voltage converter. Accordingly, the current mode buck-boost converter has fast response, and the electrical energy can be recycled and stored to the voltage source when the current mode buck-boost converter operates in down-tracking process.

Abstract: A method for forming and operating an integrated circuit, including providing a substrate; forming a bottom electrode over the substrate, wherein the bottom electrode is in or over a lowest metallization layer over the substrate; forming a blocking layer over the substrate; forming a charge-trapping layer over the blocking layer; forming an insulation layer over the charge-trapping layer; forming a control gate over the insulation layer; forming a tunneling layer over the control gate; and forming a top electrode over the tunneling layer.

Abstract: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Abstract: A method for forming and operating an integrated circuit, including providing a substrate; forming a bottom electrode over the substrate, wherein the bottom electrode is in or over a lowest metallization layer over the substrate; forming a blocking layer over the substrate; forming a charge-trapping layer over the blocking layer; forming an insulation layer over the charge-trapping layer; forming a control gate over the insulation layer; forming a tunneling layer over the control gate; and forming a top electrode over the tunneling layer.

Abstract: A capacitance sensing circuit for a touch panel includes an analog capacitance-detecting circuit, a PWM-to-digital circuit and a self-calibration circuit. The analog capacitance-detecting circuit detects the capacitance of the touch panel based on a charging current, and converts the detected capacitance into a PWM control signal. The PWM-to-digital circuit converts the PWM control signal into a sensing count value based on a clock signal. The self-calibration circuit adjusts the value of the charging current or the frequency of the clock signal according to the difference between the range of the sensing count value and a predetermined detecting range. The predetermined detecting range can thus be adjusted for matching the range of the sensing count value.

Abstract: A multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Abstract: An integrated circuit device includes a substrate; a bottom electrode over the substrate wherein the bottom electrode is in or over a lowest metallization layer over the substrate; a blocking layer over the bottom electrode; a charge-trapping layer over the blocking layer; an insulation layer over the charge-trapping layer; a control gate over the insulation layer; a tunneling layer over the control gate; and a top electrode over the tunneling layer.

Abstract: A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.