Patents by Inventor Shijian Luo

Shijian Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748857
    Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: August 18, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Bret K. Street, Wei Zhou, Christopher J. Gambee, Jonathan S. Hacker, Shijian Luo
  • Publication number: 20200258859
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Patent number: 10741468
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10679921
    Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Patent number: 10622223
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Publication number: 20200083178
    Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Bret K. Street, Wei Zhou, Christopher J. Gambee, Jonathan S. Hacker, Shijian Luo
  • Publication number: 20200075384
    Abstract: A semiconductor device assembly that includes a semiconductor device having a first side and a second side connected to a substrate. A layer of self-depolymerizing polymer connects the semiconductor device to the substrate. The layer of self-depolymerizing layer is positioned between the first side of the semiconductor device and the substrate. The layer of self-depolymerizing polymer is configured to selectively release the substrate from the semiconductor device. The layer of self-depolymerizing polymer selectively depolymerizes to release the substrate. The substrate enables processing to occur on the second side of the semiconductor device. A material may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device. Energy may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Shijian Luo, Owen R. Fay
  • Publication number: 20200076051
    Abstract: A semiconductor device, or semiconductor device package, that includes a substrate having an antenna structure on a surface of the substrate and a wire bond that electrically connects the antenna structure to the substrate to form an antenna or a first antenna configuration. The substrate may include a second antenna structure with the wire bond connected to the second antenna structure forming a second antenna or antenna configuration. The semiconductor device may include a radio communication device electrically connected to the substrate. The antenna or antenna configuration may be tuned to the requirements of the radio communication device. The antenna configuration may be tuned by connected to different antenna structures on the surface of the substrate. The antenna configuration may be tuned by changing a length of the wire bond, changing a diameter of the wire bond, and/or changing the material of the wire bond.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Shijian Luo, Owen R. Fay
  • Patent number: 10461059
    Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michel Koopmans, Shijian Luo, David R. Hembree
  • Publication number: 20190311918
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Application
    Filed: June 10, 2019
    Publication date: October 10, 2019
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Publication number: 20190253545
    Abstract: A muffling device includes an acquisition circuit, configured to obtain reference sound wave information of a user. The muffling device includes a modulation circuit, configured to analyze an acoustic wave characteristic of the reference sound wave information to obtain a characteristic parameter of the reference sound wave information. The muffling device includes a muffling circuit, configured to generate compensated sound wave information according to the characteristic parameter of the reference sound wave information. The muffling device includes a correction circuit, configured to compare muffed sound wave information superimposed by the compensated sound wave information and the reference sound wave information with the reference sound wave information, and feed back a comparison result to the muffling circuit. The muffling circuit can adjust the compensated sound wave information according to a fed back comparison result.
    Type: Application
    Filed: September 17, 2018
    Publication date: August 15, 2019
    Inventors: Yang Yu, Jiamin Liao, Shijian Luo, Tao Luo, Heyuan Qiu, Xiaowei Liu, Haiguang Li, Fan Chen
  • Publication number: 20190229086
    Abstract: Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: SEMIgear, Inc.
    Inventors: Jian ZHANG, Joshua PINNOLIS, Shijian LUO
  • Publication number: 20190219853
    Abstract: A COA substrate, a manufacturing method therefore, a display panel, and a display device. The COA substrate includes a base substrate, a thin-film transistor provided on one side of the base substrate, and a color filter film provided on the other side of the base substrate facing away from the thin-film transistor.
    Type: Application
    Filed: May 14, 2018
    Publication date: July 18, 2019
    Inventors: Jiamin LIAO, Xi CHEN, Yao LIU, Zongxiang LI, Shijian LUO, Yang YU, Bo HU, Heyuan QIU
  • Publication number: 20190157111
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Publication number: 20190157112
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 23, 2019
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Patent number: 10283481
    Abstract: Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: May 7, 2019
    Assignee: Semigear, Inc.
    Inventors: Jian Zhang, Joshua Pinnolis, Shijian Luo
  • Publication number: 20190122950
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Publication number: 20190086863
    Abstract: A display system includes: a display screen having a first display area; a processor configured to modulate laser beams to be emitted from a laser projector according to a pre-stored holographic image data source to obtain modulated laser beams; the laser projector configured to project the modulated laser beams to create a first holographic image in front of the first display area; and at least one photodetector configured to collect first gesture information about a first gesture through which the first holographic image is controlled by a viewer. The processor is further configured to generate a first control signal according to the first gesture information, and re-modulate the laser beams to be emitted from the laser projector, so as to create a second holographic image corresponding to the first control signal.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 21, 2019
    Inventors: Qiaoni WANG, Hui CHEN, Shijian LUO, Yabin LIN, Xin XIE, Chunmei YANG, Xingming CHEN, Zhijian CHEN, Xinyu ZHANG
  • Publication number: 20190051578
    Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Patent number: 10170389
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi