Abstract: A feature of this invention is to realize a VSB modulation with a simple configuration.

Abstract: This invention provides a convenient process for manufacturing 1,3-dialkyl-2-imidazolidinones in a direct one-step reaction from industrially available alkylene carbonate, N-alkylethanolamine or 1,2-diol, which can minimize forming solid materials and be readily conducted in an industrial large-scale production with a higher yield and less byproducts. The process is characterized in that alkylene carbonate, N-alkylethanolamine or 1,2-diol is reacted with monoalkylamine and carbon dioxide, alkylcarbamate alkylamine salt, and/or 1,3-dialkylurea, by heating them at 50° C. or higher in a reactor whose area in contact with at least part of the reactants and/or products is made of a metal comprising titanium or zirconium and/or an oxide thereof or inorganic glass.

Abstract: A DC-DC converter for decreasing power consumption and quickly increasing an output voltage. The converter includes a voltage generation circuit, a switching control circuit, a current detection circuit, and a step control circuit. An output transistor performs switching to generate the output voltage of the switching control circuit. The current detection circuit is connected to the voltage generation circuit to detect a load current, which is derived from the output voltage, and to generate a detection signal. A stop control circuit maintains the output transistor in an activated state in accordance with the detection signal and stops the operation of the switching control circuit when the load current is less than or equal to the load current.

Abstract: This invention relates to the use of high density polyimide foam as insulation for electrical components.

Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral length of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

Abstract: The method for fabricating a nonvolatile semiconductor memory device comprises the step of forming an insulation film 14 on a semiconductor substrate 10; the step of introducing an impurity into the semiconductor substrate through the insulation film 14 to form a source/drain diffused region 20 and a pocket layer 18; the step of removing the insulation film 14; the step of forming a charge storage layer 28 on the semiconductor substrate 10; and forming gate electrode 40 on the charge storage layer 28 between the source/drain diffused layer 20. Whereby damage due to the ion implantation is not introduced into the charge storage layer. Thus, deterioration of cycling characteristics and data retention characteristics of the nonvolatile semiconductor memory device can be prevented.

Abstract: A non-volatile semiconductor memory device includes memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked.

Abstract: On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.

Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: A semiconductor integrated circuit includes four electrodes arranged in a matrix and a wire connecting between two electrodes which are diagonally positioned to each other and selected from the four electrodes. The two remaining electrodes are diagonally positioned to each other across the wire, and have a side thereof facing the wire and extending in parallel to a longitudinal direction of the wire.

Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral length of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

Abstract: On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.

Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

Abstract: A non-volatile semiconductor memory device includes memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked.

Abstract: A current charged into or discharged from a phase-compensating capacitor C1 in an output circuit is controlled by a level shift circuit so that the current is kept constant for input signals inputted to the input terminals IN+ and IN- of a differential amplifier circuit, and also a current charged into or discharged from a phase-compensating capacitor C2 is controlled by the current correcting circuit so that the current become equal to a constant current controlled by the level shift circuit, namely to a current charged into or discharged from the phase-compensating capacitor C1. Therefore, even if a quickly rising or falling signal is inputted into the differential amplifier circuit, the MOS transistor MP11 or MN11 is not set in an offset state, which prevents generation of an overshoot or an undershot in the output terminal.

Abstract: Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.

Abstract: It is an object to obtain a semiconductor device capable of changing a delay time of an output signal of a PLL circuit with respect to an external clock signal after installed in a system. An external clock signal is inputted to an input terminal (1.) An address value is inputted to an input terminal (3.) A decoder (9) selects one of a plurality of delay times in a voltage-controlled oscillator (8) according to the address value. The phase of a signal outputted to an output terminal (2) is delayed with respect to the external clock signal at the input terminal (1) by the delay time selected. Accordingly, it is possible to change the delay time of the output signal of the PLL circuit with respect to the external clock signal after installation in a system.

Abstract: An improved process for producing a light-absorbing chalcopyrite film is disclosed, which comprises the steps of: applying at least one solution containing at least either of (a) an organic compound of a metal in Group 1B of the periodic table and (b) an organic compound of a metal in Group 3B of the periodic table on a substrate at least once to thereby form a thin film containing the organic compound (a) and the organic compound (b); heating the thin film in a reducing or inert gas atmosphere to convert the thin film into a thin metal film comprising the Group 1B metal and the Group 3B metal; and heating the thin metal film in an atmosphere containing either an element in Group 6B of the periodic table or a compound thereof to thereby convert the thin metal film into a thin chalcopyrite film.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: A vector operation data path (3) in a vector calculator is composed of a cumulative data selection unit (5) and a cumulative calculator (6). The cumulative data selection unit (5) outputs cumulative data Z(1) to Z(n) which are time series data on the basis of operation data A and operation data Y, sequentially to the cumulative calculator (6). A selector (66) in the cumulative calculator (6) outputs selected data S(i) by selecting one of differential data {Z(i)-Z(i+1)}, differential data {Z(i)-Z(i+2)} and cumulative data Z(i). The selected data S(i) is applied to an absolute value circuit (67) and a square circuit (68), and the obtained square data SQ(i) is given to an accumulator (69), and the accumulator (69) determines the cumulative value.