Abstract: Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

Abstract: In order to generate zigzag addresses for Discrete Cosine Transformation DCT data arranged in the form of a square matrix, row differentials (.DELTA.y) and column differentials (.DELTA.x) being differentials of row addresses (y) and column addresses (x) are previously stored to be successively read out (steps S12 and S13). The row differentials (.DELTA.y) and the column differentials (.DELTA.x) are added to the row addresses (y) and the column addresses (x) respectively, to newly obtain zigzag addresses (steps S14 and S15). Thus, the amount data to be stored can be reduced. Further, it is possible to further reduce the amount of data to be stored by compressing data through regularity of the row differentials (.DELTA.y) and the column differentials (.DELTA.x).

Abstract: Maintenance information is collected by a sensor on an electric power cable installed in a manhole. The information is transmitted to a radio transmitter which is positioned in a vicinity of a bottom plane of an inner lid in an opening of the manhole. The information is transmitted by the radio transmitter, and received by a receiving antenna mounted on a bottom plane of the inner lid. On a top plane of the inner lid, an electrode, a connecting lead or a transmitting antenna is provided to be connected to the receiving antenna by an impedance matching circuit. The information is supplied to an outer lid in the opening of the manhole by the opening of the manhole by the electrode using a spatial coupling capacitance relative to the outer lid, or the connecting lead directly connected to the outer lid. Thus, the information is transmitted as a radio signal by the outer lid functioning as an antenna. Otherwise, the information is radiated below the outer lid by the transmitting antenna.

Abstract: A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value.

Abstract: The DC-DC converter is disclosed, which has an output terminal connected to an external load, and produces a desired output voltage at the output terminal. An output capacitor in the converter has a first electrode connected to the output terminal and a second electrode. The charge/discharge regulator controls electrical connection between a DC power supply and the output capacitor to permit the capacitor to be charged or discharged. The DC-DC converter includes a first detecting circuit for detecting a change in the output voltage at the output terminal, and a second detecting circuit for detecting a variable load current flowing into the converter from the load via the output terminal.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: In a layout designing method for an LSI by a CMOS standard cell method, layout cells (standard layout patterns) which respectively correspond to logical function units are selected from a library. In this selection, the respective layout cells are selected from the library as patterns which are divided into p-type layout cells and n-type layout cells. The p-type layout cells and the n-type layout cells are arranged in accordance with a predetermined logical circuit diagram. Interconnection patterns for interconnecting the p-type layout cells and for interconnecting the n-type layout cells are arranged in accordance with the logical circuit diagram. An excessive interconnection region can be minimized, and efficient interconnections can be achieved. Therefore, an occupied plane area can be reduced in the layout design.

Abstract: A DC-DC converter includes first and second capacitors coupled in parallel, a switching part for controlling the first and second capacitors so that the first capacitor is charged by an input voltage and the second capacitor is charged by a discharging of the first capacitor, an output voltage being obtained at one end of the second capacitor, and the switching part including a discharge path through which the second capacitor is discharged. An output voltage detection units detects the output voltage and determines whether or not the output voltage satisfies a predetermined condition. A discharge path breaking units breakes the discharge path when the output voltage detection unit determines that the output voltage satisfies the predetermined condition, so that the first capacitor is prevented from being discharged through discharge path.

Abstract: The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.

Abstract: A logic circuit outputs a logic signal in response to set inputs and a reset input. This logic signal is applied to output terminals through a latch circuit. When outputs Q and Q of the RS flip-flop maintain a previous state, the latch circuit is activated by a control signal applied from an OR gate to hold a previous logic signal received from the logic circuit. Thus, the logic circuit and latch circuit are arranged on a signal path from input terminals to output terminals. These logic circuit and latch circuit do not include a series connection of transistors and, therefore, is operable at high speed in response to the inputs. Consequently, the outputs Q and Q have excellent response characteristics relative to the set and reset inputs, to enable a high-speed operation.

Abstract: A semiconductor integrated circuit device comprises a general purpose unit having a general purpose function and a specific unit for a specific use of the semiconductor integrated circuit device. In addition, the semiconductor integrated circuit device has structure in which a plurality of layers each having an integrated circuit formed therein are stacked in a three-dimensional manner. Specific unit layers are formed on the surface of the layer having the general purpose unit formed therein by different manufacturing processes.

Abstract: A priority order decomposing apparatus converting binary data of a plurality of bits into data wherein "1"s other than "1" of the bit whose priority order is the highest are removed, a circuit for checking whether or not "1" exists is installed for each group of bits taken as a unit of converting process. When "1" exists, this is transmitted directly to the low-order-bit side to immediately set the lower-order bits to "0". This permits the operating speed to be made faster.

Abstract: A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flip-flop through gates controlling propagation of the other output of the RS flip-flop, so that the final clock frequency is variable by switching control of each gate, whereby a pulse width of each single-phase clock is defined by a delay duration of a delay circuit, thereby not depending on wave forms of the external clock and also the gates connected between the respective single-phase pulse generating circuits are switching-controlled to enable the frequency of the output clock to be variable.

Abstract: An absolute value comparator for differences comprising a first subtracter (1a) and a second subtracter (1b) each of which performs subtraction of n-bit digital values, a controller (8) for receiving most significant bit (MSB) carry output (g) from the first subtracter (1a) and MSB carry output (h) from the second subtracter (1b) to decide coincidence/incoincidence of the said signs as well as the sign of the output (f) from the second subtracter (1b), a first selecter (10a) for selectively passing either the output (e) from the first subtracter (1a) or a digital value obtained by inverting all bits of the output (e) responsive to a sign coincidence/incoincidence detecting signal (t) from the controller (8), a full adder (7) for receiving the sign coincidence/incoincidence detecting signal (u) from the controller (8) in its carry input terminal for the LSB stage to perform addition of output (q) from the least significant bit first selecter (10a) and the output (f) from the second subtracter (1b) to output a

Abstract: Signal generating means formed by variable line delay circuits 6 and 9 and dot delay circuits 7 and 8 receives a series of signal sample of a composite color television signal sampled in synchronism with a chrominance subcarrier at a frequency four times the chrominance subcarrier frequency and generates simultaneously a sample signal at a specified sampled point for separating a luminance signal and a chrominance signal and sampled signals at four sample points adjacent to the specified sample point, namely, four sampled points on the upper, lower, right and left sides of the specified sample point. A comparing and determining circuit 10 compares and determines a direction in which there is little change in the picture, based on the sampled signals at the adjacent sample points. Based on the result of determination of the comparing and determining circuit 10, a selector 11 selects and provides two sampled signals 110 and 111 existing in a region where there is little change in the picture.

Abstract: A fluorine-containing copolymer comprising monomeric units of:(a) tetrafluoroethylene,(b) 8 to 15% by weight of hexafluoropropene on the basis of the weight of the copolymer, and(c) 0.2 to 2% by weight of a fluoroalkyl vinyl ether of the formula:CF.sub.2 .dbd.CF--O--(CF.sub.2).sub.n --CF.sub.2 Xwherein X is hydrogen or fluorine, and n is an integer of 3 to 9, on the basis of the weight of the copolymer, which has good moldability and improved stress crack resistance and flex resistance when formed as an article such as a film.

Abstract: A fluorine-containing copolymer comprising monomeric units of(a) tetrafluoroethylene,(b) 8 to 15% by weight of hexafluoropropene on the basis of the weight of the copolymer, and(c) 0.2 to 2% by weight of a fluoroalkyl vinyl ether of the formula:CF.sub.2 .dbd.CF--O--(CF.sub.2).sub.n --CF.sub.2 X (I)wherein X is hydrogen or fluorine, and n is an integer of 3 to 9 on the basis of the weight of the copolymer, which has improved stress crack resistance, and flex resistance as well as good moldability.

Abstract: Mixture of tetrafluoroethylene/hexafluoropropylene (TFE/HFP) copolymers comprising 5 to 20% by weight of hexafluoropropylene, the specific melt viscosity at 380.degree. C. of which is from 1.times.10.sup.4 to 60.times.10.sup.4 poise,(a) the melt flow ratio being at least 3.5, and(b) the zero strength time (ZST, second) at 380.degree. C. satisfying the following equation:ZST.gtoreq.1/3x.sup.2 +17x+107wherein x is (specific melt viscosity).times.10.sup.-4 having an improved extrudability, particularly an improved extrusion speed. These mixtures of copolymers contain a high specific melt viscosity portion and a low specific melt viscosity portion.