Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

Abstract: There is provided an information processing device including an image acquisition unit that acquires a captured image of a real space from an image capture device, a setting unit that sets, in association with the real space, an augmented reality space that virtually augments the real space depicted in the captured image, the augmented reality space differing according to related information that relates to the captured image, and a control unit that causes an image of a virtual object placed for each user within the augmented reality space to be displayed on a screen.

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

Abstract: One aspect of the present invention relates to a resin composition comprising a curable resin and a curing agent, which is used for forming an inter-wiring layer insulating layer in contact with a copper wiring.

Abstract: Reliability of a semiconductor device is improved. A resist pattern having an opening in a first region where a memory transistor is formed and covering other regions is prepared. Next, by ion implantation using this resist pattern as a mask, a channel region is formed in a surface of a semiconductor substrate in the first region, and a nitrogen-introduction portion is formed inside the channel region. Next, the resist pattern is removed. Then, a gate insulating film having a charge storage layer is formed on the semiconductor substrate in the first region, and a gate electrode is formed on the gate insulating film.

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

Abstract: A siloxane compound containing structures represented by the following general formulae (1) and (2): wherein R1 and R2 independently represent a hydrogen atom, a halogen atom, an alkyl group having from 1 to 3 carbon atoms, a halogenated alkyl group, a thiol group, an acetyl group, a hydroxyl group, a sulfonic acid group, a sulfoalkoxyl group having from 1 to 3 carbon atoms, or an alkoxyl group having from 1 to 3 carbon atoms; x and y independently represent an integer of from 0 to 4; and A represents a single bond or an azomethine group, an ester group, an amide group, an azoxy group, an azo group, an ethylene group, or an acetylene group, and wherein R3 and R4 independently represent an alkyl group, a phenyl group, or a substituted phenyl group; and n represents an integer of from 1 to 100.

Abstract: A radio communication apparatus includes a receiving unit configured to receive information controlling a timing at which an access request for accessing an access destination over a network is to be executed. The radio communication apparatus also includes a control unit configured to control execution of the access request with a timing controlled based at least in part on the information. An associated method, medium and an information processing apparatus are also described.

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

Abstract: An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell.

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film.

Abstract: There is provided an image processing apparatus and method and a program which enable more accurate estimation of a pose. A matching unit performs matching processing on the basis of a detection result of a feature point from an input image and a three-dimensional map indicating a position of a landmark in real space, and a pose estimating unit estimates a pose on the basis of a result of the matching processing. A three-dimensional map updating unit updates the three-dimensional map on the basis of a three-dimensional shape model indicating a position and a shape of a recognition target, a detection result of the feature point from the input image and an estimation result of the pose so that only a portion of the recognition target is registered as the landmark. The present technology can be applied to a wearable information terminal apparatus.

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film.

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

Abstract: A radio communication apparatus includes a receiving unit configured to receive information controlling a timing at which an access request for accessing an access destination over a network is to be executed. The radio communication apparatus also includes a control unit configured to control execution of the access request with a timing controlled based at least in part on the information. An associated method, medium and an information processing apparatus are also described.

Abstract: There is provided an information processing apparatus to present, to a user, an additional image, which is a virtual object, in a manner superimposed on a real-space image at a position corresponding to a viewpoint in the real space, the image processing apparatus including a processing unit configured to display an additional image corresponding to a viewpoint of a user in the real world, and guide the user to the vicinity of the viewpoint in the real world where the additional image has been acquired.