Patents by Inventor Shinji Omori

Shinji Omori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050142462
    Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.
    Type: Application
    Filed: February 11, 2005
    Publication date: June 30, 2005
    Inventors: Shinji Omori, Shigeru Moriya
  • Publication number: 20050124078
    Abstract: A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided.
    Type: Application
    Filed: March 20, 2003
    Publication date: June 9, 2005
    Applicant: Sony Corp.
    Inventors: Shinji Omori, Kaoru Koike, Shigeru Moriya, Isao Ashida
  • Publication number: 20050014076
    Abstract: A method of generating mask distortion data capable of improving accuracy of distortion measurement, an exposure method using the same and a method of producing a semiconductor device, wherein a production mask is produced by a first thin film formed with a predetermined pattern, and a positional accuracy measurement mask is produced by forming second positional accuracy measurement marks at substantially same positions as those of the first positional accuracy measurement marks on a mask blanks having a second thin film, positions of the second positional accuracy measurement marks and third positional accuracy measurement marks of the positional accuracy measurement mask are measured, a correlation function of the both are calculated, positions of the first positional accuracy measurement marks of the production mask are measured, and mask distortion data on the first thin film of the production mask is generated by using the correlation function.
    Type: Application
    Filed: May 19, 2004
    Publication date: January 20, 2005
    Inventor: Shinji Omori
  • Publication number: 20050008948
    Abstract: A complementary division method able to suppress a pattern deformation by wet washing, having the steps of determining a definite division length able to suppress the pattern deformation when wet washing to a width and distance of a pattern that is assumed the pattern deformation over an elasticity limit is easiest given by wet washing in advance, dividing the entire line-and-space patterns at the determined division length in the longitudinal direction to divide suitably the line-and-space pattern by a simple algorithm, and further providing a method of producing a mask and program.
    Type: Application
    Filed: July 7, 2004
    Publication date: January 13, 2005
    Inventors: Yoko Watanabe, Shinji Omori
  • Publication number: 20040224243
    Abstract: A mask decreased in warping and having a high positioning precision, provided with at least a substrate aperture formed at a portion of a silicon substrate, a first silicon oxide film formed at one surface of the silicon substrate, a single crystal silicon layer formed on the first silicon layer and the substrate aperture, at least one aperture formed at a portion of the single crystal silicon layer on the substrate aperture and passing an exposure beam, a stress controlling layer formed on another surface of the silicon substrate having internal stress for flattening warping of the silicon substrate due to at least compressive stress of the first silicon oxide film; a method of producing the same, a mask blank decreased in warping, and a method of producing the same.
    Type: Application
    Filed: April 29, 2004
    Publication date: November 11, 2004
    Applicant: Sony Corporation
    Inventors: Masaki Yoshizawa, Shinji Omori
  • Publication number: 20040209174
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 21, 2004
    Inventors: Shigeru Moriya, Shinji Omori
  • Publication number: 20040209175
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 21, 2004
    Inventors: Shigeru Moriya, Shinji Omori
  • Patent number: 6787785
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: September 7, 2004
    Assignee: Sony Corporation
    Inventors: Shigeru Moriya, Shinji Omori
  • Publication number: 20040086790
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Application
    Filed: October 21, 2003
    Publication date: May 6, 2004
    Inventors: Shigeru Moriya, Shinji Omori
  • Publication number: 20030137024
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 24, 2003
    Inventors: Shigeru Moriya, Shinji Omori
  • Patent number: 5675363
    Abstract: In an apparatus for displaying image data created by a computer according to the random-scan system, until the created display data is read out and displayed, in the time of buffering a buffer memory for temporarily storing the display data, the data is divided into plural blocks based on the display coordinate information added to the display data and is thus stored. When reading the data, the data is read out and displayed in sequence from blocks adjacent to each other.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: October 7, 1997
    Assignee: Hitachi Denshi Kabushiki Kaisha
    Inventor: Shinji Omori
  • Patent number: 4644582
    Abstract: Two images to be registered are divided into a plurality of image portions. A standard point for the registration is extracted for each of the image portions divided. Coordinate transformations between two images for the registration are conducted for each image portion by using the standard point extracted. The coordinate values transformed between the image portions are smoothed in the case that they discretely change so that they may be smoothly connected.
    Type: Grant
    Filed: January 24, 1984
    Date of Patent: February 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Morishita, Shinji Omori, Shimbu Yamagata, Tetsuo Yokoyama, Koichi Sano, Akira Ogushi