Patents by Inventor Shinya Kamimura

Shinya Kamimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010015428
    Abstract: A horizontal transfer section is formed on a P-type semiconductor substrate. A floating diffusion layer for receiving signal charges from the horizontal transfer section and a detector MOSFET for detecting any potential change of the floating diffusion layer are further formed. This detector MOSFET has a gate electrode in which an opening is formed. The gate electrode extends toward the floating diffusion layer and the opening is positioned above the floating diffusion layer. As a result, a solid-state image sensor constituted as above, can reduce the area of the floating diffusion layer and can detect signal charges at high sensitivity.
    Type: Application
    Filed: December 19, 2000
    Publication date: August 23, 2001
    Inventor: Shinya Kamimura
  • Patent number: 6081015
    Abstract: In a semiconductor device, in order to protect an interior of the device, protective circuits are provided. The protective circuits include a first circuit connected between the first terminal and a negative potential line, a second circuit connected between the first terminal and a ground potential line, and a third circuit connected between the ground potential line and a second terminal. The first circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the negative potential line, and a gate connected with the first terminal or the negative potential line. The second circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the ground potential line, and a gate connected with the first terminal or the ground potential line.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: June 27, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shinya Kamimura
  • Patent number: 5357129
    Abstract: There is provided a solid state imaging device having high-sensitivity, low-noise characteristics by reducing electrostatic capacity relating to interconnection. The solid state imaging device includes a photoelectric conversion section, a transfer section, a floating diffusion layer for receiving signal charges from the transfer section, and an output transistor having a gate electrode connected to the floating diffusion layer via an interconnection. A source and a drain of the output transistor are provided commonly within a flat p-type well of relatively thin concentration in which the photoelectric conversion section, the transfer section, and the floating diffusion layer are also provided.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: October 18, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shinya Kamimura