Patents by Inventor Shoji Matsumoto
Shoji Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7564695Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.Type: GrantFiled: June 23, 2008Date of Patent: July 21, 2009Assignee: Canon Kabushiki KaishaInventor: Shoji Matsumoto
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Patent number: 7531495Abstract: A cleaning agent or a rinsing agent having no flash point which comprises a chlorine-free fluorine-containing compound having a vapor pressure at 20° C. of 1.33×103 Pa or more and one or more components having a vapor pressure at 20° C. less than 1.33×103 Pa and optionally an additive such as an antioxidant; a method for cleaning which comprises cleaning with the cleaning agent and rinsing and/or vapor cleaning utilizing a vapor being generated by boiling the cleaning agent or a condensate thereof; a method for separating a soil which comprises contacting a cleaning agent in a cleaning tank with a condensate of the vapor of the cleaning agent in a soil separating tank, to thereby continuously separate and remove a soil contained in the cleaning agent; and a cleaning apparatus.Type: GrantFiled: May 8, 2001Date of Patent: May 12, 2009Assignee: Asahi Kasei Kabushiki KaishaInventors: Kazuo Kabashima, Kenichi Kato, Shoji Matsumoto
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Publication number: 20090119692Abstract: An optical pickup device includes an optical system unit, a circuit board to control the optical system unit, and send and receive signals, a housing to place the optical system unit and the circuit board, and a flexible printed circuit board to connect electrically with the circuit board, extend to an outside from the housing, and fold back an extended portion, an extended direction of which is changed, in which the flexible printed circuit board is folded back so as to be faced to a side surface of the housing positioned at an extended proximal portion of the flexible printed circuit board, and a dead space of an optical disc apparatus to be mounted with the optical pickup device can be effectively used without making the apparatus large and thick, taking an inner space widely.Type: ApplicationFiled: November 6, 2008Publication date: May 7, 2009Inventors: Shinya Fujimori, Nobuyuki Maeda, Tetsuo Ito, Shoji Ueda, Shinya Iizaka, Akihiro Ooba, Shoji Matsumoto, Katsuhiko Kimura, Toru Shibata
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Publication number: 20090016031Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.Type: ApplicationFiled: June 23, 2008Publication date: January 15, 2009Applicant: CANON KABUSHIKI KAISHAInventor: Shoji Matsumoto
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Publication number: 20070195473Abstract: Impedance mismatching points such as a VIA and a connector on a differential line between a differential driver element and a differential receiver element are arranged in predetermined positions. That is, the impedance mismatching points are arranged in such positions that a transmission time of a digital signal transmitted through a main differential line becomes (integral multiple of UI) ±0.5×Trf, whereby noises are generated within the rise and fall times of a signal to be able to maintain an excellent waveform of the signal.Type: ApplicationFiled: October 11, 2006Publication date: August 23, 2007Inventor: Shoji Matsumoto
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Publication number: 20070079641Abstract: The invention is directed to provide a forming method and a forming apparatus that are, without extending a processing time compared with the conventional practice, capable of sufficiently lubricating a formed object and forming at safety without the lubricant igniting under pressure. In an extruding apparatus, a workpiece is successively transferred to a series of press stages, a conveying unit successively transferring the workpiece is provided with a nozzle for spraying the workpiece with lubricant, and the workpiece and the nozzle are located in fixed relative positions to each other in spraying the workpiece with the lubricant.Type: ApplicationFiled: November 25, 2004Publication date: April 12, 2007Inventors: Yoshihisa Doi, Masayoshi Sakakibara, Shoji Matsumoto, Koichi Goto
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Publication number: 20030168079Abstract: A cleaning agent or a rinsing agent having no flash point which comprises a chlorine-free fluorine-containing compound having a vapor pressure at 20° C. of 1.33×103 Pa or more and one or more components having a vapor pressure at 20° C. less than 1.33×103 Pa and optionally an additive such as an antioxidant; a method for cleaning which comprises cleaning with the cleaning agent and rinsing and/or vapor cleaning utilizing a vapor being generated by boiling the cleaning agent or a condensate thereof; a method for separating a soil which comprises contacting a cleaning agent in a cleaning tank with a condensate of the vapor of the cleaning agent in a soil separating tank, to thereby continuously separate and remove a soil contained in the cleaning agent; and a cleaning apparatus.Type: ApplicationFiled: November 29, 2002Publication date: September 11, 2003Inventors: Kazuo Kabashima, Kenichi Kato, Shoji Matsumoto
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Patent number: 6007673Abstract: A semiconductor substrate which is placed on a bottom electrode inside a chamber is dry-etched by creating plasma inside the chamber. By making the average surface roughness Ra of the bottom surface of a quartz-top plate placed on the bottom electrode be in a range of 0.2 to 5 .mu.m, adhesion between the quartz-top plate and the deposits caused by the dry etching is enhanced, and the number of particles suspended in the chamber is reduced. Furthermore, the function of enhancing the adhesion of deposits can be maintained even after cleaning of the quartz-top plate. As a result, the number of particles which adhere onto the semiconductor substrate is reduced and the semiconductor substrate can be processed in an extremely clean atmosphere.Type: GrantFiled: October 1, 1997Date of Patent: December 28, 1999Assignee: Matsushita Electronics CorporationInventors: Shunsuke Kugo, Hideo Nikoh, Tomoyuki Sasaki, Hideo Ichimura, Daihei Kajiwara, Shoji Matsumoto, Satoshi Nakagawa
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Patent number: 5989929Abstract: A reactor is composed of a lower frame of a chamber, a quartz dome, an upper electrode, an 0 ring, and the like. A lower electrode and a substrate as a workpiece to be processed thereon are disposed in the reactor. The temperature of the quartz dome is maintained at a temperature of 180.degree. C. or higher by means of a heater. Fluorocarbon gas such as C.sub.2 F.sub.6 gas or C.sub.4 F.sub.8 gas is introduced into the reactor through a gas inlet and RF power from a first RF power source is applied to an antenna coil to produce a plasma and thereby etch an oxide film on the substrate. By heating the quartz dome to a high temperature, a deposit which hinders the release of oxygen from a wall face is prevented from being attached and the deposit on the bottom of the hole which causes an etch stop during processing is removed with oxygen. This prevents the etch stop during an etching process for forming a deep hole.Type: GrantFiled: July 21, 1998Date of Patent: November 23, 1999Assignee: Matsushita Electronics CorporationInventors: Hideo Nikoh, Shinichi Imai, Nobuhiro Jiwari, Satoshi Nakagawa, Shoji Matsumoto, Yoji Bito
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Patent number: 5599424Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.Type: GrantFiled: December 13, 1995Date of Patent: February 4, 1997Assignee: Matsushita Electronics CorporationInventors: Shoji Matsumoto, Yoshihisa Nagano, Yasuhiro Shimada, Yasufumi Izutsu
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Patent number: 5527729Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.Type: GrantFiled: March 29, 1995Date of Patent: June 18, 1996Assignee: Matsushita Electronics CorporationInventors: Shoji Matsumoto, Yoshihisa Nagano, Yasuhiro Shimada, Yasufumi Izutsu
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Patent number: 5500386Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.Type: GrantFiled: June 7, 1995Date of Patent: March 19, 1996Assignee: Matsushita Electronics CorporationInventors: Shoji Matsumoto, Hideo Nikou, Satoshi Nakagawa
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Patent number: 5492855Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped. A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained a S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.Type: GrantFiled: December 27, 1994Date of Patent: February 20, 1996Assignee: Matsushita Electronics CorporationInventors: Shoji Matsumoto, Hideo Nikou, Satoshi Nakagawa
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Patent number: 5485344Abstract: A charging method for charging a photosensitive material of, for example, the photosensitive drum of an electrophotographic copying apparatus is accomplished by bringing an endless electrically conducting flexible sheet containing a brush roller into physical contact with the surface of the photosensitive material and applying a voltage to the electrically conducting flexible sheet. The electrically conducting flexible sheet is a laminate of a first resistance layer positioned on the side of the brush roller and a second resistance layer positioned on the outer surface of the first resistance layer. The second resistance layer has an electric resistance greater than that of the first resistance layer.Type: GrantFiled: September 27, 1993Date of Patent: January 16, 1996Assignee: Mita Industrial Co., Ltd.Inventors: Shoji Matsumoto, Masanori Matsuda, Eiji Goto, Akinori Nishida, Takeshi Hori
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Patent number: 5446615Abstract: An electrifying method which uses a electrifying a material wherein the contact-type electrifying member comprises a flexible and electrically conducting endless sheet and a brush which supports said endless sheet and imparts a pressing force thereto at a position where said endless sheet is in contact with the material to be electrified, said endless sheet which is impressed with an electrification voltage is driven or is moved at a speed which is substantially in synchronism with the material to be electrified, and the brush and the endless sheet are maintained at dissimilar speeds.Type: GrantFiled: March 26, 1993Date of Patent: August 29, 1995Assignee: Mita Industrial Co., Ltd.Inventors: Shoji Matsumoto, Masanori Matsuda, Eiji Goto, Akinori Nishida, Teruaki Higashiguchi, Isao Iwagawa
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Patent number: 5048179Abstract: An IC mounting method and its resulting structure, such as an IC card is provided. An IC card includes a metal plate formed with at least one hole, and an IC chip is located fixed in position in the hole with a filler material filling the gap between the hole and the IC chip. An interconnect pattern is provided on the plate with an electrically insulating film sandwiched therebetween, and the interconnect pattern is in electrical contact with a contact pad of the IC chip. Preferably, the surface of the IC chip on which the contact pad is provided is substantially flush with one surface of the plate. When an electrically insulating film is fixedly attached to a substrate having a hole, in which an IC chip is fixedly provided, by an adhesive agent, the material of the film is selected to be similar to the material of the adhesive agent.Type: GrantFiled: February 14, 1990Date of Patent: September 17, 1991Assignee: Ricoh Company, Ltd.Inventors: Masahiro Shindo, Toshikazu Yoshimizu, Kenichi Kurihara, Shunpei Tamaki, Toshio Kawakami, Yukio Kadowaki, Shoji Matsumoto
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Patent number: 5041847Abstract: A thermal head comprising a substrate, a heat-resistant dielectric resin layer disposed on the substrate, a resistor layer disposed on the resin layer for forming a plurality of heating elements and an electrode layer disposed on the resistor layer for forming electrodes connecting to the heating elements. A protection film covers an end of the substrate and each end of the layers which is substantially in the same plane as the substrate end.Type: GrantFiled: August 21, 1990Date of Patent: August 20, 1991Assignee: Ricoh Company, Ltd.Inventors: Shoji Matsumoto, Daisuke Kosaka, Masaaki Yoshida, Hidehito Kitakado, Kenji Fujita
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Patent number: 4884051Abstract: A semiconductor diffusion type force sensing apparatus includes a plate-like semiconductor substrate formed by a single crystal material, and a plurality of sensing elements each constituted by a substantially rectangular impurity-diffused region formed in the semiconductor substrate. The sensing elements have an electric resistance variable in accordance with a deformation thereof due to an external force exerted on the semiconductor substrate. The sensing elements are arranged in a direction in which a longitudinal direction of each of the sensing elements coincides with a crystal orientation of the semiconductor substrate having an external value of a longitudinal piezoresistance coefficient of the impurity-diffused region.Type: GrantFiled: July 5, 1988Date of Patent: November 28, 1989Assignee: Ricoh Company, Ltd.Inventors: Junichi Takahashi, Daisuke Kosaka, Hirotoshi Eguchi, Shoji Matsumoto, Takashi Akahori, Hiroshi Yamazaki, Kouji Izumi
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Patent number: 4440488Abstract: A cleaning device for an image-carrying member includes an elastic blade having a proximal end fixed to a holder and a terminal end held against the image-carrying member for removing toner from the image-carrying member upon movement of the image-carrying member. The terminal end of the blade flexes to extend forward in the direction of movement of the image-carrying member at an angle of .alpha. to a line tangential to a surface of the image carrying member rearward of a contact point between the terminal end of the blade and the image carrying member with respect to the direction of movement thereof. The blade has an axis passing through the proximal end of the blade and extending at an angle of .theta. to the tangent rearward of the contact point with respect to the direction of movement of the image-carrying member. The angles .alpha. and .theta. are selected to meet the following relationship:.theta.>90.degree.>.alpha..Type: GrantFiled: August 25, 1982Date of Patent: April 3, 1984Assignee: Mita Industrial Company LimitedInventors: Takashi Maekawa, Shoji Matsumoto, Toshikazu Matsui
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Patent number: 4430410Abstract: In a method and apparatus for developing a latent electrostatic image formed on the surface of an image-bearing material by applying a powdery developer thereto, which includes magnetically retaining a layer of a relatively conductive one-component developer having a resistivity of not more than 10.sup.13 ohms-cm on the surface of a developer-retaining member, and bringing the developer on the surface of the developer-retaining member into contact with the surface of the image bearing material, the improvement wherein the developer-retaining member has a resistance, measured by a point-plane resistance measuring method in an environment kept at a temperature of 20.degree. C. and a humidity of 50%, of from 3.times.10.sup.7 ohms to 1.times.10.sup.10 ohms. The improved method makes possible good development without causing a background fog or a tail effect.Type: GrantFiled: August 27, 1979Date of Patent: February 7, 1984Assignee: Mita Industrial Co., Ltd.Inventors: Tatsuo Aizawa, Shoji Matsumoto, Kaoru Sakata, Toshikazu Matsui, Akira Fushida, Toshimitsu Ikeda, Nobuyoshi Hisao