Abstract: A movable device simultaneously enabling reduction of size down to the submicron level, higher speed operation, a streamlined production process, low costs, and greater reliability. A movable device provided with bottom electrodes and a basic conductive layer fixed to a substrate, an elastic shaft of a carbon nanotube with a bottom end fixed on the basic conductive layer and standing up, and a top structure including a top electrode spaced away from the bottom electrode and fixed to a top end of the elastic shaft, wherein when applying voltage between a bottom electrode and the top electrode, the top electrode displaces relatively to the bottom electrodes within an allowable range of elastic deformation of the elastic shaft.

Abstract: A movable device simultaneously enabling reduction of size down to the submicron level, higher speed operation, a streamlined production process, low costs, and greater reliability. A movable device provided with bottom electrodes and a basic conductive layer fixed to a substrate, an elastic shaft of a carbon nanotube with a bottom end fixed on the basic conductive layer and standing up, and a top structure including a top electrode spaced away from the bottom electrode and fixed to a top end of the elastic shaft, wherein when applying voltage between a bottom electrode and the top electrode, the top electrode displaces relatively to the bottom electrodes within an allowable range of elastic deformation of the elastic shaft.

Abstract: The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semiconductor device also has drift layers formed in the surface layer of the semiconductor substrate between the gate electrodes and one of the impurity diffusion layers as a same conduction type as the impurity diffusion layers. The gate electrodes are made of metal including aluminum, and each is formed in an overhang shape. The semiconductor device can provide an LDMOS transistor enhanced in maximum transmission frequency and power gain and capable of a high-frequency operation with high efficiency as a basic element of a high-frequency power amplifier.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: The semiconductor device comprises one layer including interconnections 32a to 32d formed above a substrate 10, and an insulation layer 34 formed over said one layer, a cavity 40 being included in said one layer. The dummy interconnection is removed by etching, whereby the layer can be planarized while the parasitic capacitance between the interconnections can be made small. Furthermore, the dielectric constant of the air in the cavity is much smaller than that of the inter-layer insulation film, whereby in comparison with the parasitic constant of the case where the inter-layer insulation film are formed simply between interconnections, the parasitic constant between the interconnections of the present invention can be made smaller.

Abstract: The semiconductor device comprises: an insulation film 72 formed over a silicon substrate 10, an insulation film 78 formed on the insulation film 72 and having opening 82, and conductor 84 formed at least in the opening 82. Cavity 88 having the peripheral edges conformed to a configuration of the opening 82 is formed in the insulation film 72. The cavity 88 is formed in the region between the electrodes or the regions between the interconnection layers so as to decrease the dielectric constant between the electrodes or between the interconnection layers, whereby the parasitic capacitances of the region between the electrodes or the region between the interconnection layers can be drastically decreased, and consequently the semiconductor device can have higher speed.

Abstract: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. Of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: Substitution reaction between polysilicon and Al (aluminum) is utilized. Namely, polysilicon films are formed by patterning at first as in the related art, and after an Al film is formed on an interlayer insulating film to be in contact with the polysilicon films, the polysilicon films in the interlayer insulating film 9 are replaced with Al by heat treatment. By patterning, gate electrodes constituted of Al low in gate parasite resistance and high in mobility is formed.

Abstract: A capacitor 19 comprises a lower electrode 14 formed on a substrate 10, an upper electrode 18 opposed to the lower electrode, and a capacitor dielectric film 16 formed between the lower electrode and the upper electrode, in which at least one of the lower electrode and the upper electrodes is an electrode of a metal substituted layer. The lower electrodes of polysilicon are formed, and then after the high-temperature heat processing for improving film quality of the capacitor dielectric film has been performed, the lower electrodes of polysilicon is substituted with aluminum to form the lower electrodes of aluminum, whereby aluminum, which cannot withstand the heat processing for improving film quality of the capacitor dielectric film can be used as a material of the lower electrodes. Thus, capacitors having good high-speed response can be formed.

Abstract: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

Abstract: The anti-fuse comprises a substitutable layer 14, an interconnection layer 20 connected to the substitutable layer, and the interconnection layer contains metal atoms which can be substituted with constituent atoms of the substitutable layer. The anti-fuse can be changed from the non-conduction state to the conduction state at a relatively low temperature of 300° C. to 600° C., and by application of not so intense laser beams, the anti-fuse can be changed from the non-conduction state to the conduction state. The anti-fuse can be changed from the non-conduction state to the conduction state by using an inexpensive equipment, which can realize decrease of fabrication costs and accordingly inexpensive semiconductor devices can be provided.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. Of the capacitor. Short circuit between the capacitor and the bit line can be prevented.