Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: A method for fabricating a semiconductor device including a step of forming an interconnection having the upper surface covered with an insulation film on a base substrate, a step of sequentially depositing an insulation film and an insulation film on the base substrate with the interconnection formed on, a step of etching the insulation film with the insulation film as a stopper to form openings in a region containing a region where the interconnection is formed, and the step of etching the insulation film in the opening to form sidewall insulation films of the insulation film on the side walls of the interconnection and to form contact holes to be connected to the base substrate in alignment with the interconnection.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

Abstract: A capacitor 19 comprises a lower electrode 14 formed on a substrate 10, an upper electrode 18 opposed to the lower electrode, and a capacitor dielectric film 16 formed between the lower electrode and the upper electrode, in which at least one of the lower electrode and the upper electrodes is an electrode of a metal substituted layer. The lower electrodes of polysilicon are formed, and then after the high-temperature heat processing for improving film quality of the capacitor dielectric film has been performed, the lower electrodes of polysilicon is substituted with aluminum to form the lower electrodes of aluminum, whereby aluminum, which cannot withstand the heat processing for improving film quality of the capacitor dielectric film can be used as a material of the lower electrodes. Thus, capacitors having good high-speed response can be formed.

Abstract: A semiconductor device comprising: a storage electrode having a side wall forward tapered; a capacitor dielectric film formed on the side wall of the storage electrode; and a plate electrode formed on the side wall of the storage electrode with the capacitor dielectric film interposing therebetween, the plate electrode having a side wall inversely tapered.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A capacitor 19 comprises a lower electrode 14 formed on a substrate 10, an upper electrode 18 opposed to the lower electrode, and a capacitor dielectric film 16 formed between the lower electrode and the upper electrode, in which at least one of the lower electrode and the upper electrodes is an electrode of a metal substituted layer. The lower electrodes of polysilicon are formed, and then after the high-temperature heat processing for improving film quality of the capacitor dielectric film has been performed, the lower electrodes of polysilicon is substituted with aluminum to form the lower electrodes of aluminum, whereby aluminum, which cannot withstand the heat processing for improving film quality of the capacitor dielectric film can be used as a material of the lower electrodes. Thus, capacitors having good high-speed response can be formed.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: The semiconductor device comprises one layer including interconnections 32a to 32d formed above a substrate 10, and an insulation layer 34 formed over said one layer, a cavity 40 being included in said one layer. The dummy interconnection is removed by etching, whereby the layer can be planarized while the parasitic capacitance between the interconnections can be made small. Furthermore, the dielectric constant of the air in the cavity is much smaller than that of the inter-layer insulation film, whereby in comparison with the parasitic constant of the case where the inter-layer insulation film are formed simply between interconnections, the parasitic constant between the interconnections of the present invention can be made smaller.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: The anti-fuse comprises a substitutable layer 14, an interconnection layer 20 connected to the substitutable layer, and the interconnection layer contains metal atoms which can be substituted with constituent atoms of the substitutable layer. The anti-fuse can be changed from the non-conduction state to the conduction state at a relatively low temperature of 300° C. to 600° C., and by application of not so intense laser beams, the anti-fuse can be changed from the non-conduction state to the conduction state. The anti-fuse can be changed from the non-conduction state to the conduction state by using an inexpensive equipment, which can realize decrease of fabrication costs and accordingly inexpensive semiconductor devices can be provided.

Abstract: A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: Insulation films 45, 56 having a contact hole 58 are formed on a substrate. A dummy plug 62 is formed in the contact hole 58. Insulation films 64, 66 are formed on the insulation film 56. An opening 70 for exposing at least a part of the dummy plug 62 is formed in the insulation films 64, 66. The dummy plug 62 is selectively removed through the opening 70. A storage electrode 72 is formed in the contact hole 58 and the opening 70. The insulation film 66 is selectively removed. A dielectric film 74 and a plate electrode are formed on the storage electrode 72. Whereby, without an extra support for supporting the storage electrode 72, the storage electrode 72 is prevented form falling down or peeling off, and defective contact and breakage of the lower structure due to disalignment can be precluded.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.