Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: Insulation films 45, 56 having a contact hole 58 are formed on a substrate. A dummy plug 62 is formed in the contact hole 58. Insulation films 64, 66 are formed on the insulation film 56. An opening 70 for exposing at least a part of the dummy plug 62 is formed in the insulation films 64, 66. The dummy plug 62 is selectively removed through the opening 70. A storage electrode 72 is formed in the contact hole 58 and the opening 70. The insulation film 66 is selectively removed. A dielectric film 74 and a plate electrode are formed on the storage electrode 72. Whereby, without an extra support for supporting the storage electrode 72, the storage electrode 72 is prevented form falling down or peeling off, and defective contact and breakage of the lower structure due to disalignment can be precluded.

Abstract: A semiconductor device comprises: a lower contact electrode 1; an adhesion improving layer 3 formed on the lower contact electrode 1; and a capacitor including a lower electrode 4 in a projected structure formed on the adhesion improving layer 3, a capacitor dielectric film 5 formed on the lower electrode 4, and an upper electrode 6 formed on the capacitor dielectric film 5, in which a gap is formed on a sidewall of the adhesion improving layer 3. The gap is at least partially left as a cavity 7. The gap insulates the upper electrode 6 and the adhesion improving layer 3 by the cavity 7.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: The semiconductor device comprises: an insulation film 72 formed over a silicon substrate 10, an insulation film 78 formed on the insulation film 72 and having opening 82, and conductor 84 formed at least in the opening 82. Cavity 88 having the peripheral edges conformed to a configuration of the opening 82 is formed in the insulation film 72. The cavity 88 is formed in the region between the electrodes or the regions between the interconnection layers so as to decrease the dielectric constant between the electrodes or between the interconnection layers, whereby the parasitic capacitances of the region between the electrodes or the region between the interconnection layers can be drastically decreased, and consequently the semiconductor device can have higher speed.

Abstract: A semiconductor device comprising: a storage electrode having a side wall forward taped; a capacitor dielectric film formed on the side wall of the storage electrode; and a plate electrode formed on the side wall of the storage electrode with the capacitor dielectric film interposing therebetween, the plate electrode having a side wall inversely tapered.

Abstract: The method for fabricating the semiconductor device comprises the steps of: forming an insulation film 56 above a substrate 10; forming an opening 60 in the insulation film 56 down to the substrate 10; forming a plate electrode 62 on at least a side wall of the opening 60; removing the insulation film 56 to form an opening 68 having a side wall surrounded by a plate electrode 62; forming a capacitor dielectric film 70 on at least a side wall of the opening 68; and forming a storage electrode 72 on the capacitor dielectric film 70. Whereby electric characteristics between the electrode, etc. in the below structure and the storage electrode are prevented from deterioration in high-temperature thermal processing in the step of forming the capacitor dielectric film.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A process of etching a semiconductor substrate and forming a trench which becomes a positioning mark on the semiconductor substrate, forming a burying film to fill the trench, forming a mask layer having an aperture to expose the trench, introducing an impurity to the trench with the mask layer used as the mask, and recessing the burying film in the trench which becomes the positioning mark.

Abstract: Insulation films 45, 56 having a contact hole 58 are formed on a substrate. A dummy plug 62 is formed in the contact hole 58. Insulation films 64, 66 are formed on the insulation film 56. An opening 70 for exposing at least a part of the dummy plug 62 is formed in the insulation films 64, 66. The dummy plug 62 is selectively removed through the opening 70. A storage electrode 72 is formed in the contact hole 58 and the opening 70. The insulation film 66 is selectively removed. A dielectric film 74 and a plate electrode are formed on the storage electrode 72. Whereby, without an extra support for supporting the storage electrode 72, the storage electrode 72 is prevented form falling down or peeling off, and defective contact and breakage of the lower structure due to disalignment can be precluded.

Abstract: The method for fabricating the semiconductor device comprises the steps of: forming an insulation film 56 above a substrate 10; forming an opening 60 in the insulation film 56 down to the substrate 10; forming a plate electrode 62 on at least a side wall of the opening 60; removing the insulation film 56 to form an opening 68 having a side wall surrounded by a plate electrode 62; forming a capacitor dielectric film 70 on at least a side wall of the opening 68; and forming a storage electrode 72 on the capacitor dielectric film 70. Whereby electric characteristics between the electrode, etc. in the below structure and the storage electrode are prevented from deterioration in high-temperature thermal processing in the step of forming the capacitor dielectric film.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: A drying oven for curing paint applied to a vehicle comprising a housing, radiant heat panel located on the side walls of the housing, a conveyor for carrying a vehicle through the housing and a convection heater unit positioned at a height below the conveyor such that heat from the convection heater is directed onto the under floor of the vehicle passing through the housing on the conveyor. In a first embodiment, the convection heater unit includes a feed pipe positioned below the conveyor and a plurality of nozzles extending from the feed pipe for directing hot air onto the under floor of the vehicle. In a second embodiment, a plurality of heat ducts are located below and to the side of the conveyor, each heat duct having an opening directed at the under floor of the vehicle on the conveyor for directing hot air onto the under floor of the vehicle.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor.A conductive layer is laminated through an insulating layer in a region surrounded by the ring-shaped emitter region provided a little toward the inner periphery of the base region, a conductive side wall is formed on the sides of the conductive layer and the insulating layer, and the ring-shaped emitter region and the conductive layer are connected through the conductive side wall. A metallic emitter electrode is connected to the conductive layer.