Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105137
    Abstract: A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a purality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10zA/?m at room termperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100zA/?m per micrometer in the channel width.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20240107865
    Abstract: Manufacturing equipment for a light-emitting device with which steps from formation to sealing of a light-emitting element can be successively performed is provided. With the manufacturing equipment for a light-emitting device, a deposition step, a lithography step, and an etching step for forming an organic EL element and a sealing step by formation of a protective layer can be successively performed. Accordingly, a downscaled organic EL element with high luminance and high reliability can be formed. Moreover, the manufacturing equipment can have an in-line system where apparatuses are arranged in the order of process steps for the light-emitting device, resulting in high throughput manufacturing.
    Type: Application
    Filed: January 28, 2022
    Publication date: March 28, 2024
    Inventors: Shingo EGUCHI, Hiroki ADACHI, Kenichi OKAZAKI, Yasumasa YAMANE, Naoto KUSUMOTO, Kensuke YOSHIZUMI, Shunpei YAMAZAKI
  • Publication number: 20240107861
    Abstract: A display device capable of displaying high-quality images can be provided. A display device includes a first light-emitting element, a second light-emitting element, a first protective layer, a second protective layer, and a gap. The first light-emitting element includes a first lower electrode, a first EL layer over the first lower electrode, a first upper electrode over the first EL layer, and the second light-emitting element includes a second lower electrode, a second EL layer over the second lower electrode, and a second upper electrode over the second EL layer. The first light-emitting element and the second light-emitting element are adjacent to each other. The first protective layer is provided over the first light-emitting element and the second light-emitting element and includes a region in contact with the side surface of the first EL layer and the side surface of the second EL layer. The second protective layer is provided over the first protective layer.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Ryota HODO, Yuichi YANAGISAWA
  • Publication number: 20240107845
    Abstract: Provided is a high-resolution or high-definition display apparatus. The display apparatus includes a first light-emitting element, a second light-emitting element, and a sidewall. The first and second light-emitting elements each include a pixel electrode, a first light-emitting layer over the pixel electrode, an intermediate layer over the first light-emitting layer, a second light-emitting layer over the intermediate layer, and a common electrode over the second light-emitting layer. That is, the first and second light-emitting elements can have tandem structures. The pixel electrode, the first light-emitting layer, the intermediate layer, and the second light-emitting layer are separately provided between the light-emitting elements. The first light-emitting element and the second light-emitting element are adjacent to each other, and the sidewall is provided between the first light-emitting element and the second light-emitting element.
    Type: Application
    Filed: February 2, 2022
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Yasumasa YAMANE, Ryota HODO
  • Publication number: 20240105853
    Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA
  • Publication number: 20240105855
    Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hitoshi KUNITAKE
  • Publication number: 20240105733
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Toshinari SASAKI, Junichiro SAKATA, Masashi TSUBUKU
  • Publication number: 20240107799
    Abstract: A novel functional panel that is highly convenient, useful, or reliable is provided. The functional panel includes a base material and a pair of pixels, and the base material covers the pair of pixels and has a light-transmitting property. The pair of pixels includes one pixel and another pixel, and the one pixel includes a light-emitting device and a first microlens. The light-emitting device emits light toward the base material, and the first microlens is interposed between the base material and the light emission and converges light. The first microlens includes a first surface and a second surface; the second surface is closer to the light-emitting device than the first surface is; and the second surface has a smaller radius of curvature than the first surface. The other pixel includes a photoelectric conversion device and a second microlens. The second microlens is interposed between the base material and the photoelectric conversion and converges external light incident from the base material side.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Inventors: Shunpei YAMAZAKI, Daiki NAKAMURA, Ryo HATSUMI, Rai SATO, Shingo EGUCHI, Koji KUSUNOKI
  • Publication number: 20240107854
    Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Kensuke YOSHIZUMI
  • Patent number: 11942370
    Abstract: A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoki Okuno, Tetsuya Kakehata, Hiroki Komagata, Yuji Egi
  • Patent number: 11942555
    Abstract: A semiconductor device with favorable electric characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulating layer, the first conductive layer is connected to the oxide semiconductor layer, and the second conductive layer is connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 11942132
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11943929
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11940702
    Abstract: A novel composite oxide semiconductor which can be used in a transistor including an oxide semiconductor film is provided. In the composite oxide semiconductor, a first region and a second region are mixed. The first region includes a plurality of first clusters containing In and oxygen as main components. The second region includes a plurality of second clusters containing Zn and oxygen as main components. The plurality of first clusters have portions connected to each other. The plurality of second clusters have portions connected to each other.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20240094574
    Abstract: A touch panel which is thin, has a simple structure, or is easily incorporated into an electronic device is provided. The touch panel includes a first substrate, a second substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, liquid crystal, and an FPC. The first conductive layer has a function of a pixel electrode. The second conductive layer has a function of a common electrode. The third and fourth conductive layers each have a function of an electrode of a touch sensor. The FPC is electrically connected to the fourth conductive layer. The first, second, third, and fourth conductive layers and the liquid crystal are provided between the first and second substrates. The first, second, and third conductive layers are provided over the first substrate. The FPC is provided over the first substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Hajime KIMURA, Shunpei YAMAZAKI
  • Publication number: 20240095507
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 21, 2024
    Inventors: Takahiko ISHIZU, Takayuki IKEDA, Atsuo ISOBE, Atsushi MIYAGUCHI, Shunpei YAMAZAKI
  • Publication number: 20240092655
    Abstract: A novel method for forming a positive electrode active material is provided. In the method for forming a positive electrode active material, a cobalt source and an additive element source are mixed to form an acidic solution; the acidic solution and an alkaline solution are made to react to form a cobalt compound; the cobalt compound and a lithium source are mixed to form a mixture; and the mixture is heated. The additive element source is a compound containing one or more selected from gallium, aluminum, boron, nickel, and indium.
    Type: Application
    Filed: January 21, 2022
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Yusuke YOSHITANI, Yohei MOMMA, Kunihiro FUKUSHIMA, Tetsuya KAKEHATA
  • Publication number: 20240096243
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. The first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. The second support can pivot on an axis extending in the one direction with respect to the first support.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Shingo EGUCHI, Taiki NONAKA, Daiki NAKAMURA, Nozomu SUGISAWA, Kazuhiko FUJITA, Shunpei YAMAZAKI
  • Publication number: 20240094768
    Abstract: To provide an electronic device capable of a variety of display. To provide an electronic device capable of being operated in a variety of ways. An electronic device includes a display device and first to third surfaces. The first surface includes a region in contact with the second surface, the second surface includes a region in contact with the third surface, and the first surface includes a region opposite to the third surface. The display device includes first to third display regions. The first display region includes a region overlapping with the first surface, the second display region includes a region overlapping with the second surface, and the third display region includes a region overlapping with the third surface. The first display region has a larger area than the third display region.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA
  • Publication number: 20240099054
    Abstract: A highly reliable light-emitting device is provided. Damage to an element due to externally applied physical power is suppressed. Alternatively, in a process of pressure-bonding of an FPC, damage to a resin and a wiring which are in contact with a flexible substrate due to heat is suppressed. A neutral plane at which stress-strain is not generated when a flexible light-emitting device including an organic EL element is deformed, is positioned in the vicinity of a transistor and the organic EL element. Alternatively, the hardness of the outermost surface of a light-emitting device is high. Alternatively, a substrate having a coefficient of thermal expansion of 10 ppm/K or lower is used as a substrate that overlaps with a terminal portion connected to an FPC.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Semiconductor EnergyL aboratoryCo., Ltd.
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI