Patents by Inventor Shyam Surthi
Shyam Surthi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150206886Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.Type: ApplicationFiled: December 12, 2014Publication date: July 23, 2015Inventors: Jaydip Guha, Shyam Surthi
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Patent number: 9070584Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.Type: GrantFiled: May 24, 2013Date of Patent: June 30, 2015Assignee: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 9070767Abstract: Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region.Type: GrantFiled: November 14, 2013Date of Patent: June 30, 2015Assignee: Micron Technology, Inc.Inventor: Shyam Surthi
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Patent number: 9054216Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: GrantFiled: June 30, 2014Date of Patent: June 9, 2015Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 9041099Abstract: The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer.Type: GrantFiled: April 11, 2011Date of Patent: May 26, 2015Assignee: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Sheng-Wei Yang
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Publication number: 20150123280Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 9012303Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.Type: GrantFiled: October 21, 2014Date of Patent: April 21, 2015Assignee: Nanya Technology CorporationInventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
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Publication number: 20150037961Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
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Patent number: 8946018Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.Type: GrantFiled: August 21, 2012Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi
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Publication number: 20150014766Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Lars P. Heineck, Shyam Surthi, Jaydip Guha
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Patent number: 8901631Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.Type: GrantFiled: March 11, 2013Date of Patent: December 2, 2014Assignee: Nanya Technology CorporationInventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
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Publication number: 20140346652Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.Type: ApplicationFiled: May 24, 2013Publication date: November 27, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 8871589Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.Type: GrantFiled: September 18, 2013Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventors: Lars P Heineck, Shyam Surthi, Jaydip Guha
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Publication number: 20140315364Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: June 30, 2014Publication date: October 23, 2014Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Publication number: 20140264754Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: MICRON TECHNOLOGY, INC.Inventor: Shyam Surthi
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Publication number: 20140252532Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
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Patent number: 8790977Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: GrantFiled: November 14, 2013Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Publication number: 20140070306Abstract: Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: Micron Technology, Inc.Inventor: Shyam Surthi
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Publication number: 20140073100Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: Micron Technology, Inc.Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
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Patent number: 8667928Abstract: Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.Type: GrantFiled: April 13, 2011Date of Patent: March 11, 2014Assignee: Micron Technology, Inc.Inventor: Shyam Surthi